Index: /webserver/example/EasyWEB/easyweb.c =================================================================== --- /webserver/example/EasyWEB/easyweb.c (revision 9) +++ /webserver/example/EasyWEB/easyweb.c (revision 10) @@ -22,11 +22,13 @@ #include "EMAC.h" // Ethernet packet driver #include "tcpip.h" // easyWEB TCP/IP stack -#include // Keil: Register definition file for LPC2368 +#include "LPC23xx.h" // Keil: Register definition file for LPC2368 #include "webpage.h" // webside for our HTTP server (HTML) //void main(void) -int main(void) +void main(void) { + + TCPLowLevelInit(); Index: /webserver/example/EasyWEB/ARM RAM Debug/Retarget.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/Retarget.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/Retarget.d (revision 10) @@ -0,0 +1,2 @@ +ARM\ RAM\ Debug/Retarget.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/Retarget.c Index: /webserver/example/EasyWEB/ARM RAM Debug/easyweb.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/easyweb.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/easyweb.d (revision 10) @@ -0,0 +1,11 @@ +ARM\ RAM\ Debug/easyweb.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/easyweb.c \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdio.h \ + /home/phil/CrossWorks_ARM_1_7/include/string.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/easyweb.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/LPC23xx.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/webpage.h Index: /webserver/example/EasyWEB/ARM RAM Debug/tcpip.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/tcpip.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/tcpip.d (revision 10) @@ -0,0 +1,6 @@ +ARM\ RAM\ Debug/tcpip.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.c \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/include/string.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h LPC23xx.h Index: /webserver/example/EasyWEB/ARM RAM Debug/VIC_PL192_irq_handler.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/VIC_PL192_irq_handler.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/VIC_PL192_irq_handler.d (revision 10) @@ -0,0 +1,3 @@ +ARM\ RAM\ Debug/VIC_PL192_irq_handler.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_PL192_irq_handler.s \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_irq_handler.s Index: /webserver/example/EasyWEB/ARM RAM Debug/catch_irqs.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/catch_irqs.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/catch_irqs.d (revision 10) @@ -0,0 +1,2 @@ +ARM\ RAM\ Debug/catch_irqs.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/catch_irqs.cpp Index: /webserver/example/EasyWEB/ARM RAM Debug/EMAC.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/EMAC.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/EMAC.d (revision 10) @@ -0,0 +1,4 @@ +ARM\ RAM\ Debug/EMAC.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.c \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h LPC23xx.h Index: /webserver/example/EasyWEB/ARM RAM Debug/Philips_LPC230X_Startup.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/Philips_LPC230X_Startup.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/Philips_LPC230X_Startup.d (revision 10) @@ -0,0 +1,4 @@ +ARM\ RAM\ Debug/Philips_LPC230X_Startup.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/Philips_LPC230X_Startup.s \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2000.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2368.h Index: /webserver/example/EasyWEB/ARM RAM Debug/VIC_PL192.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/VIC_PL192.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/VIC_PL192.d (revision 10) @@ -0,0 +1,6 @@ +ARM\ RAM\ Debug/VIC_PL192.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_PL192.c \ + /home/phil/CrossWorks_ARM_1_7/include/ctl_api.h \ + /home/phil/CrossWorks_ARM_1_7/include/libarm.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h Index: /webserver/example/EasyWEB/ARM RAM Debug/crt0.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/crt0.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/crt0.d (revision 10) @@ -0,0 +1,2 @@ +ARM\ RAM\ Debug/crt0.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../source/crt0.s Index: /webserver/example/EasyWEB/ARM RAM Debug/EasyWeb.map =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/EasyWeb.map (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/EasyWeb.map (revision 10) @@ -0,0 +1,624 @@ +Archive member included because of file (symbol) + +/home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + ARM RAM Debug/LPC230x.o (liblpc2000_lpc23xx_get_cclk) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) (__udivsi3) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + ARM RAM Debug/easyweb.o (memcpy) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + ARM RAM Debug/tcpip.o (memset) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + ARM RAM Debug/tcpip.o (memcmp) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + ARM RAM Debug/easyweb.o (sprintf) +/home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) (__vfprintf) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) (strlen) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) (__hex_uc) + +Allocating common symbols +Common symbol size file + +TCPTimer 0x1 ARM RAM Debug/easyweb.o +HTTPBytesToSend 0x4 ARM RAM Debug/easyweb.o +TCPRxDataCount 0x2 ARM RAM Debug/easyweb.o +HTTPStatus 0x1 ARM RAM Debug/easyweb.o +TCPTxDataCount 0x2 ARM RAM Debug/easyweb.o +RecdFrameIP 0x4 ARM RAM Debug/easyweb.o +RemoteMAC 0x6 ARM RAM Debug/easyweb.o +TCPStateMachine 0x4 ARM RAM Debug/easyweb.o +TCPUNASeqNr 0x4 ARM RAM Debug/easyweb.o +TCPLocalPort 0x2 ARM RAM Debug/easyweb.o +_RxTCPBuffer 0x100 ARM RAM Debug/easyweb.o +TCPFlags 0x1 ARM RAM Debug/easyweb.o +RecdFrameMAC 0x6 ARM RAM Debug/easyweb.o +RecdIPFrameLength 0x2 ARM RAM Debug/easyweb.o +PWebSide 0x4 ARM RAM Debug/easyweb.o +RemoteIP 0x4 ARM RAM Debug/easyweb.o +LastFrameSent 0x4 ARM RAM Debug/easyweb.o +TCPRemotePort 0x2 ARM RAM Debug/easyweb.o +TxFrame2Size 0x1 ARM RAM Debug/easyweb.o +TCPAckNr 0x4 ARM RAM Debug/easyweb.o +TransmitControl 0x1 ARM RAM Debug/easyweb.o +TxFrame1Size 0x2 ARM RAM Debug/easyweb.o +ISNGenHigh 0x2 ARM RAM Debug/easyweb.o +_TxFrame2 0x4a ARM RAM Debug/easyweb.o +RecdFrameLength 0x2 ARM RAM Debug/easyweb.o +_TxFrame1 0x236 ARM RAM Debug/easyweb.o +TCPSeqNr 0x4 ARM RAM Debug/easyweb.o +RetryCounter 0x1 ARM RAM Debug/easyweb.o +SocketStatus 0x1 ARM RAM Debug/easyweb.o + +Memory Configuration + +Name Origin Length Attributes +UNPLACED_SECTIONS 0xffffffff 0x00000000 xw +AHB_Peripherals 0xffe00000 0x00200000 xw +Battery_RAM 0xe0084000 0x00000800 xw +APB_Peripherals 0xe0000000 0x00200000 xw +USB_RAM 0x7fd00000 0x00002000 xw +Ethernet_RAM 0x7fe00000 0x00004000 xw +SRAM 0x40000000 0x00008000 xw +FLASH 0x00000000 0x00080000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + + 0xffe00000 __AHB_Peripherals_segment_start__ = 0xffe00000 + 0x00000000 __AHB_Peripherals_segment_end__ = 0x0 + 0xe0084000 __Battery_RAM_segment_start__ = 0xe0084000 + 0xe0084800 __Battery_RAM_segment_end__ = 0xe0084800 + 0xe0000000 __APB_Peripherals_segment_start__ = 0xe0000000 + 0xe0200000 __APB_Peripherals_segment_end__ = 0xe0200000 + 0x7fd00000 __USB_RAM_segment_start__ = 0x7fd00000 + 0x7fd02000 __USB_RAM_segment_end__ = 0x7fd02000 + 0x7fe00000 __Ethernet_RAM_segment_start__ = 0x7fe00000 + 0x7fe04000 __Ethernet_RAM_segment_end__ = 0x7fe04000 + 0x40000000 __SRAM_segment_start__ = 0x40000000 + 0x40008000 __SRAM_segment_end__ = 0x40008000 + 0x00000000 __FLASH_segment_start__ = 0x0 + 0x00080000 __FLASH_segment_end__ = 0x80000 + 0x00000400 __STACKSIZE__ = 0x400 + 0x00000100 __STACKSIZE_IRQ__ = 0x100 + 0x00000100 __STACKSIZE_FIQ__ = 0x100 + 0x00000000 __STACKSIZE_SVC__ = 0x0 + 0x00000000 __STACKSIZE_ABT__ = 0x0 + 0x00000000 __STACKSIZE_UND__ = 0x0 + 0x00000400 __HEAPSIZE__ = 0x400 + 0x40000000 __vectors_load_start__ = __SRAM_segment_start__ + +.vectors 0x40000000 0x38 + 0x40000000 __vectors_start__ = . + *(.vectors .vectors.*) + .vectors 0x40000000 0x38 ARM RAM Debug/Philips_LPC230X_Startup.o + 0x40000000 _vectors + 0x40000038 __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors)) + 0x00000001 . = ASSERT (((__vectors_end__ >= __SRAM_segment_start__) && (__vectors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .vectors is too large to fit in SRAM memory segment) + 0x40000038 __fast_load_start__ = (__vectors_end__ ALIGN 0x4) + +.fast 0x40000038 0x0 + 0x40000038 __fast_start__ = . + *(.fast .fast.*) + 0x40000038 __fast_end__ = (__fast_start__ + SIZEOF (.fast)) + 0x00000001 . = ASSERT (((__fast_end__ >= __SRAM_segment_start__) && (__fast_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .fast is too large to fit in SRAM memory segment) + 0x40000038 __init_load_start__ = (__fast_end__ ALIGN 0x4) + +.init 0x40000038 0x2e0 + 0x40000038 __init_start__ = . + *(.init .init.*) + *fill* 0x40000038 0x8 00 + .init 0x40000040 0x1d0 ARM RAM Debug/crt0.o + 0x40000040 __start + 0x40000040 _start + .init 0x40000210 0x108 ARM RAM Debug/Philips_LPC230X_Startup.o + 0x40000210 reset_handler + 0x400002fc undef_handler + 0x40000304 pabort_handler + 0x40000308 dabort_handler + 0x40000300 swi_handler + 0x4000030c fiq_handler + 0x40000318 __init_end__ = (__init_start__ + SIZEOF (.init)) + 0x00000001 . = ASSERT (((__init_end__ >= __SRAM_segment_start__) && (__init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .init is too large to fit in SRAM memory segment) + 0x40000318 __text_load_start__ = (__init_end__ ALIGN 0x4) + +.text 0x40000318 0x4458 + 0x40000318 __text_start__ = . + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + .text 0x40000318 0x474 ARM RAM Debug/easyweb.o + 0x40000688 InsertDynamicValues + 0x400005ec GetAD0Val + 0x400003cc HTTPServer + 0x40000318 main + .glue_7 0x4000078c 0x0 ARM RAM Debug/easyweb.o + .glue_7t 0x4000078c 0x0 ARM RAM Debug/easyweb.o + .text 0x4000078c 0xcac ARM RAM Debug/EMAC.o + 0x4000132c WriteFrame_EMAC + 0x40001128 StartReadFrame + 0x40000fc4 ReadFrame_EMAC + 0x4000078c write_PHY + 0x40001058 CopyFromFrame_EMAC + 0x4000082c read_PHY + 0x400011c4 EndReadFrame + 0x40001004 ReadFrameBE_EMAC + 0x4000130c Rdy4Tx + 0x400008fc rx_descr_init + 0x400010e4 DummyReadFrame_EMAC + 0x40001370 CopyToFrame_EMAC + 0x40000a2c tx_descr_init + 0x40000b48 Init_EMAC + 0x40001228 CheckFrameReceived + 0x40001288 RequestSend + .glue_7 0x40001438 0x0 ARM RAM Debug/EMAC.o + .glue_7t 0x40001438 0x0 ARM RAM Debug/EMAC.o + .text 0x40001438 0x0 ARM RAM Debug/Retarget.o + .glue_7 0x40001438 0x0 ARM RAM Debug/Retarget.o + .glue_7t 0x40001438 0x0 ARM RAM Debug/Retarget.o + .text 0x40001438 0x23ec ARM RAM Debug/tcpip.o + 0x400034f0 TCPHandleRetransmission + 0x400035e8 TCPClockHandler + 0x400034c0 TCPStopTimer + 0x40001c04 ProcessEthBroadcastFrame + 0x40001760 IsBroadcast + 0x400014d0 TCPPassiveOpen + 0x40003244 CalcChecksum + 0x4000180c DoNetworkStuff + 0x400015c4 TCPClose + 0x4000357c TCPHandleTimeout + 0x40001680 TCPTransmitTxBuffer + 0x40002c48 PrepareTCP_FRAME + 0x40002fd4 PrepareTCP_DATA_FRAME + 0x40001ee8 ProcessTCPFrame + 0x40002a10 PrepareICMP_ECHO_REPLY + 0x400028c0 PrepareARP_ANSWER + 0x40001ce0 ProcessEthIAFrame + 0x40001530 TCPActiveOpen + 0x40003440 TCPStartTimeWaitTimer + 0x40003730 WriteDWBE + 0x400036d0 WriteWBE + 0x400037c4 SwapBytes + 0x40003498 TCPRestartTimer + 0x40003698 SendFrame2 + 0x400033d4 TCPStartRetryTimer + 0x40001438 TCPLowLevelInit + 0x40001e9c ProcessICMPFrame + 0x40001650 TCPReleaseRxBuffer + 0x40003660 SendFrame1 + 0x400026e0 PrepareARP_REQUEST + .glue_7 0x40003824 0x0 ARM RAM Debug/tcpip.o + .glue_7t 0x40003824 0x0 ARM RAM Debug/tcpip.o + .text 0x40003824 0x40 ARM RAM Debug/catch_irqs.o + 0x40003824 irq_handler() + 0x40003844 swi_handler() + 0x40003834 fiq_handler() + 0x40003854 undef_handler() + .glue_7 0x40003864 0x0 ARM RAM Debug/catch_irqs.o + .glue_7t 0x40003864 0x0 ARM RAM Debug/catch_irqs.o + .text 0x40003864 0x0 ARM RAM Debug/crt0.o + .glue_7 0x40003864 0x0 ARM RAM Debug/crt0.o + .glue_7t 0x40003864 0x0 ARM RAM Debug/crt0.o + .text 0x40003864 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o + .glue_7 0x40003864 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o + .glue_7t 0x40003864 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o + .text 0x40003864 0x2fc ARM RAM Debug/LPC230x.o + 0x40003b40 ctl_get_ticks_per_second + 0x40003a48 ctl_start_timer + 0x400038ec get_uart_clk + .glue_7 0x40003b60 0x0 ARM RAM Debug/LPC230x.o + .glue_7t 0x40003b60 0x0 ARM RAM Debug/LPC230x.o + .text 0x40003b60 0x168 ARM RAM Debug/VIC_PL192.o + 0x40003c48 ctl_unmask_isr + 0x40003b60 ctl_set_isr + 0x40003c88 ctl_mask_isr + .glue_7 0x40003cc8 0x0 ARM RAM Debug/VIC_PL192.o + .glue_7t 0x40003cc8 0x0 ARM RAM Debug/VIC_PL192.o + .text 0x40003cc8 0x44 ARM RAM Debug/VIC_PL192_irq_handler.o + 0x40003cc8 irq_handler + .glue_7 0x40003d0c 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o + .glue_7t 0x40003d0c 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o + .text 0x40003d0c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .text.liblpc2000 + 0x40003d0c 0x98 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + 0x40003d0c liblpc2000_lpc23xx_get_cclk + .glue_7 0x40003da4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .glue_7t 0x40003da4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .text 0x40003da4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + *fill* 0x40003da4 0xc 00 + .text.libc 0x40003db0 0x30 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + 0x40003db0 __int32_udiv + 0x40003db0 __int32_udivmod + 0x40003db0 __udivsi3 + .glue_7 0x40003de0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .glue_7t 0x40003de0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .text 0x40003de0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .text.libc 0x40003de0 0x60 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + 0x40003de0 memcpy + .glue_7 0x40003e40 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .glue_7t 0x40003e40 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .text 0x40003e40 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .text.libc 0x40003e40 0xa0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + 0x40003e40 memset + .glue_7 0x40003ee0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .glue_7t 0x40003ee0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .text 0x40003ee0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .text.libc 0x40003ee0 0x68 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + 0x40003ee0 memcmp + .glue_7 0x40003f48 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .glue_7t 0x40003f48 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .text 0x40003f48 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .text.libc 0x40003f48 0x44 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + 0x40003f48 sprintf + .glue_7 0x40003f8c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .glue_7t 0x40003f8c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .text 0x40003f8c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .text.libc 0x40003f8c 0x780 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + 0x40004048 __vfprintf + .glue_7 0x4000470c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .glue_7t 0x4000470c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .text 0x4000470c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + *fill* 0x4000470c 0x4 00 + .text.libc 0x40004710 0x60 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + 0x40004710 strlen + .glue_7 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .glue_7t 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .text 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .text.libc 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .glue_7 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .glue_7t 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x40004770 __text_end__ = (__text_start__ + SIZEOF (.text)) + 0x00000001 . = ASSERT (((__text_end__ >= __SRAM_segment_start__) && (__text_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .text is too large to fit in SRAM memory segment) + 0x40004770 __dtors_load_start__ = (__text_end__ ALIGN 0x4) + +.dtors 0x40004770 0x0 + 0x40004770 __dtors_start__ = . + *(SORT(.dtors.*)) + *(.dtors) + 0x40004770 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) + 0x00000001 . = ASSERT (((__dtors_end__ >= __SRAM_segment_start__) && (__dtors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .dtors is too large to fit in SRAM memory segment) + 0x40004770 __ctors_load_start__ = (__dtors_end__ ALIGN 0x4) + +.ctors 0x40004770 0x0 + 0x40004770 __ctors_start__ = . + *(SORT(.ctors.*)) + *(.ctors) + 0x40004770 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) + 0x00000001 . = ASSERT (((__ctors_end__ >= __SRAM_segment_start__) && (__ctors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .ctors is too large to fit in SRAM memory segment) + 0x40004770 __data_load_start__ = (__ctors_end__ ALIGN 0x4) + +.data 0x40004770 0x0 + 0x40004770 __data_start__ = . + *(.data .data.* .gnu.linkonce.d.*) + .data 0x40004770 0x0 ARM RAM Debug/easyweb.o + .data 0x40004770 0x0 ARM RAM Debug/EMAC.o + .data 0x40004770 0x0 ARM RAM Debug/Retarget.o + .data 0x40004770 0x0 ARM RAM Debug/tcpip.o + .data 0x40004770 0x0 ARM RAM Debug/catch_irqs.o + .data 0x40004770 0x0 ARM RAM Debug/crt0.o + .data 0x40004770 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o + .data 0x40004770 0x0 ARM RAM Debug/LPC230x.o + .data 0x40004770 0x0 ARM RAM Debug/VIC_PL192.o + .data 0x40004770 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .data 0x40004770 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x40004770 __data_end__ = (__data_start__ + SIZEOF (.data)) + 0x00000001 . = ASSERT (((__data_end__ >= __SRAM_segment_start__) && (__data_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .data is too large to fit in SRAM memory segment) + 0x40004770 __rodata_load_start__ = (__data_end__ ALIGN 0x4) + +.rodata 0x40004770 0x4bc + 0x40004770 __rodata_start__ = . + *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata 0x40004770 0x494 ARM RAM Debug/easyweb.o + 0x40004770 GetResponse + 0x400047a2 SubnetMask + 0x400047a6 GatewayIP + 0x400047ac WebSide + 0x4000479e MyIP + .rodata 0x40004c04 0x6 ARM RAM Debug/tcpip.o + 0x40004c04 MyMAC + *fill* 0x40004c0a 0x2 00 + .rodata.libc 0x40004c0c 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x40004c0c __hex_uc + 0x40004c1c __hex_lc + 0x40004c2c __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) + 0x00000001 . = ASSERT (((__rodata_end__ >= __SRAM_segment_start__) && (__rodata_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .rodata is too large to fit in SRAM memory segment) + 0x40004c2c __bss_load_start__ = (__rodata_end__ ALIGN 0x4) + +.bss 0x40004c2c 0x3da + 0x40004c2c __bss_start__ = . + *(.bss .bss.* .gnu.linkonce.b.*) + .bss 0x40004c2c 0x0 ARM RAM Debug/easyweb.o + .bss 0x40004c2c 0x8 ARM RAM Debug/EMAC.o + .bss 0x40004c34 0x0 ARM RAM Debug/Retarget.o + .bss 0x40004c34 0x0 ARM RAM Debug/tcpip.o + .bss 0x40004c34 0x0 ARM RAM Debug/catch_irqs.o + .bss 0x40004c34 0x0 ARM RAM Debug/crt0.o + .bss 0x40004c34 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o + .bss 0x40004c34 0x4 ARM RAM Debug/LPC230x.o + .bss 0x40004c38 0x0 ARM RAM Debug/VIC_PL192.o + .bss 0x40004c38 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .bss 0x40004c38 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + *(COMMON) + COMMON 0x40004c38 0x3ce ARM RAM Debug/easyweb.o + 0x40004c38 TCPTimer + 0x40004c3c HTTPBytesToSend + 0x40004c40 TCPRxDataCount + 0x40004c42 HTTPStatus + 0x40004c44 TCPTxDataCount + 0x40004c46 RecdFrameIP + 0x40004c4a RemoteMAC + 0x40004c50 TCPStateMachine + 0x40004c54 TCPUNASeqNr + 0x40004c58 TCPLocalPort + 0x40004c5a _RxTCPBuffer + 0x40004d5a TCPFlags + 0x40004d5c RecdFrameMAC + 0x40004d62 RecdIPFrameLength + 0x40004d64 PWebSide + 0x40004d68 RemoteIP + 0x40004d6c LastFrameSent + 0x40004d70 TCPRemotePort + 0x40004d72 TxFrame2Size + 0x40004d74 TCPAckNr + 0x40004d78 TransmitControl + 0x40004d7a TxFrame1Size + 0x40004d7c ISNGenHigh + 0x40004d7e _TxFrame2 + 0x40004dc8 RecdFrameLength + 0x40004dca _TxFrame1 + 0x40005000 TCPSeqNr + 0x40005004 RetryCounter + 0x40005005 SocketStatus + 0x40005006 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) + 0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .bss is too large to fit in SRAM memory segment) + 0x40005008 __non_init_load_start__ = (__bss_end__ ALIGN 0x4) + +.non_init 0x40005008 0x0 + 0x40005008 __non_init_start__ = . + *(.non_init .non_init.*) + 0x40005008 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) + 0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .non_init is too large to fit in SRAM memory segment) + 0x40005008 __heap_load_start__ = (__non_init_end__ ALIGN 0x4) + +.heap 0x40005008 0x400 + 0x40005008 __heap_start__ = . + *(.heap) + 0x40005408 . = (((__heap_start__ + __HEAPSIZE__) MAX_K .) ALIGN 0x4) + *fill* 0x40005008 0x400 00 + 0x40005408 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) + 0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .heap is too large to fit in SRAM memory segment) + 0x40005408 __stack_load_start__ = (__heap_end__ ALIGN 0x4) + +.stack 0x40005408 0x400 + 0x40005408 __stack_start__ = . + *(.stack) + 0x40005808 . = (((__stack_start__ + __STACKSIZE__) MAX_K .) ALIGN 0x4) + *fill* 0x40005408 0x400 00 + 0x40005808 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) + 0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack is too large to fit in SRAM memory segment) + 0x40005808 __stack_irq_load_start__ = (__stack_end__ ALIGN 0x4) + +.stack_irq 0x40005808 0x100 + 0x40005808 __stack_irq_start__ = . + *(.stack_irq) + 0x40005908 . = (((__stack_irq_start__ + __STACKSIZE_IRQ__) MAX_K .) ALIGN 0x4) + *fill* 0x40005808 0x100 00 + 0x40005908 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq)) + 0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_irq is too large to fit in SRAM memory segment) + 0x40005908 __stack_fiq_load_start__ = (__stack_irq_end__ ALIGN 0x4) + +.stack_fiq 0x40005908 0x100 + 0x40005908 __stack_fiq_start__ = . + *(.stack_fiq) + 0x40005a08 . = (((__stack_fiq_start__ + __STACKSIZE_FIQ__) MAX_K .) ALIGN 0x4) + *fill* 0x40005908 0x100 00 + 0x40005a08 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq)) + 0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_fiq is too large to fit in SRAM memory segment) + 0x40005a08 __stack_svc_load_start__ = (__stack_fiq_end__ ALIGN 0x4) + +.stack_svc 0x40005a08 0x0 + 0x40005a08 __stack_svc_start__ = . + *(.stack_svc) + 0x40005a0c . = (((__stack_svc_start__ + __STACKSIZE_SVC__) MAX_K .) ALIGN 0x4) + 0x40005a08 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc)) + 0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_svc is too large to fit in SRAM memory segment) + 0x40005a08 __stack_abt_load_start__ = (__stack_svc_end__ ALIGN 0x4) + +.stack_abt 0x40005a08 0x0 + 0x40005a08 __stack_abt_start__ = . + *(.stack_abt) + 0x40005a0c . = (((__stack_abt_start__ + __STACKSIZE_ABT__) MAX_K .) ALIGN 0x4) + 0x40005a08 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt)) + 0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_abt is too large to fit in SRAM memory segment) + 0x40005a08 __stack_und_load_start__ = (__stack_abt_end__ ALIGN 0x4) + +.stack_und 0x40005a08 0x0 + 0x40005a08 __stack_und_start__ = . + *(.stack_und) + 0x40005a0c . = (((__stack_und_start__ + __STACKSIZE_UND__) MAX_K .) ALIGN 0x4) + 0x40005a08 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und)) + 0x40005a08 __SRAM_segment_used_end__ = ((__stack_abt_end__ ALIGN 0x4) + SIZEOF (.stack_und)) + 0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_und is too large to fit in SRAM memory segment) +START GROUP +LOAD ARM RAM Debug/easyweb.o +LOAD ARM RAM Debug/EMAC.o +LOAD ARM RAM Debug/Retarget.o +LOAD ARM RAM Debug/tcpip.o +LOAD ARM RAM Debug/catch_irqs.o +LOAD ARM RAM Debug/crt0.o +LOAD ARM RAM Debug/Philips_LPC230X_Startup.o +LOAD ARM RAM Debug/LPC230x.o +LOAD ARM RAM Debug/VIC_PL192.o +LOAD ARM RAM Debug/VIC_PL192_irq_handler.o +LOAD /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libm_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libcpp_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libdebugio_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_targetio_impl_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfscanf_long_v4t_a_le.a +END GROUP +OUTPUT(ARM RAM Debug/EasyWeb.elf elf32-littlearm) + +.debug_abbrev 0x00000000 0x585 + .debug_abbrev 0x00000000 0xec ARM RAM Debug/easyweb.o + .debug_abbrev 0x000000ec 0xf7 ARM RAM Debug/EMAC.o + .debug_abbrev 0x000001e3 0x1 ARM RAM Debug/Retarget.o + .debug_abbrev 0x000001e4 0x15f ARM RAM Debug/tcpip.o + .debug_abbrev 0x00000343 0x28 ARM RAM Debug/catch_irqs.o + .debug_abbrev 0x0000036b 0x14 ARM RAM Debug/crt0.o + .debug_abbrev 0x0000037f 0x10 ARM RAM Debug/Philips_LPC230X_Startup.o + .debug_abbrev 0x0000038f 0xc9 ARM RAM Debug/LPC230x.o + .debug_abbrev 0x00000458 0x9e ARM RAM Debug/VIC_PL192.o + .debug_abbrev 0x000004f6 0x14 ARM RAM Debug/VIC_PL192_irq_handler.o + .debug_abbrev 0x0000050a 0x23 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_abbrev 0x0000052d 0x23 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_abbrev 0x00000550 0x34 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_abbrev 0x00000584 0x1 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_info 0x00000000 0x1efc + .debug_info 0x00000000 0x6e8 ARM RAM Debug/easyweb.o + .debug_info 0x000006e8 0x4bf ARM RAM Debug/EMAC.o + .debug_info 0x00000ba7 0x0 ARM RAM Debug/Retarget.o + .debug_info 0x00000ba7 0xad0 ARM RAM Debug/tcpip.o + .debug_info 0x00001677 0x11e ARM RAM Debug/catch_irqs.o + .debug_info 0x00001795 0x98 ARM RAM Debug/crt0.o + .debug_info 0x0000182d 0xb4 ARM RAM Debug/Philips_LPC230X_Startup.o + .debug_info 0x000018e1 0x1ff ARM RAM Debug/LPC230x.o + .debug_info 0x00001ae0 0x299 ARM RAM Debug/VIC_PL192.o + .debug_info 0x00001d79 0xb4 ARM RAM Debug/VIC_PL192_irq_handler.o + .debug_info 0x00001e2d 0x32 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_info 0x00001e5f 0x32 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_info 0x00001e91 0x6b /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_info 0x00001efc 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_line 0x00000000 0xa68 + .debug_line 0x00000000 0xd4 ARM RAM Debug/easyweb.o + .debug_line 0x000000d4 0x116 ARM RAM Debug/EMAC.o + .debug_line 0x000001ea 0x1d ARM RAM Debug/Retarget.o + .debug_line 0x00000207 0x27f ARM RAM Debug/tcpip.o + .debug_line 0x00000486 0x72 ARM RAM Debug/catch_irqs.o + .debug_line 0x000004f8 0xd2 ARM RAM Debug/crt0.o + .debug_line 0x000005ca 0xf1 ARM RAM Debug/Philips_LPC230X_Startup.o + .debug_line 0x000006bb 0xe5 ARM RAM Debug/LPC230x.o + .debug_line 0x000007a0 0xcf ARM RAM Debug/VIC_PL192.o + .debug_line 0x0000086f 0x9f ARM RAM Debug/VIC_PL192_irq_handler.o + .debug_line 0x0000090e 0x68 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_line 0x00000976 0x69 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_line 0x000009df 0x6c /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_line 0x00000a4b 0x1d /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_frame 0x00000000 0xc94 + .debug_frame 0x00000000 0xc0 ARM RAM Debug/easyweb.o + .debug_frame 0x000000c0 0x2d0 ARM RAM Debug/EMAC.o + .debug_frame 0x00000390 0x53c ARM RAM Debug/tcpip.o + .debug_frame 0x000008cc 0xc0 ARM RAM Debug/catch_irqs.o + .debug_frame 0x0000098c 0xec ARM RAM Debug/LPC230x.o + .debug_frame 0x00000a78 0x94 ARM RAM Debug/VIC_PL192.o + .debug_frame 0x00000b0c 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .debug_frame 0x00000b2c 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .debug_frame 0x00000b4c 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .debug_frame 0x00000b6c 0x2c /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_frame 0x00000b98 0x40 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_frame 0x00000bd8 0x9c /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_frame 0x00000c74 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + +.debug_loc 0x00000000 0xb0a + .debug_loc 0x00000000 0xa8 ARM RAM Debug/easyweb.o + .debug_loc 0x000000a8 0x2a0 ARM RAM Debug/EMAC.o + .debug_loc 0x00000348 0x4ec ARM RAM Debug/tcpip.o + .debug_loc 0x00000834 0xa8 ARM RAM Debug/catch_irqs.o + .debug_loc 0x000008dc 0xd2 ARM RAM Debug/LPC230x.o + .debug_loc 0x000009ae 0x7e ARM RAM Debug/VIC_PL192.o + .debug_loc 0x00000a2c 0x1f /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_loc 0x00000a4b 0x37 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_loc 0x00000a82 0x88 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_pubnames + 0x00000000 0x768 + .debug_pubnames + 0x00000000 0x26f ARM RAM Debug/easyweb.o + .debug_pubnames + 0x0000026f 0x135 ARM RAM Debug/EMAC.o + .debug_pubnames + 0x000003a4 0x27a ARM RAM Debug/tcpip.o + .debug_pubnames + 0x0000061e 0x54 ARM RAM Debug/catch_irqs.o + .debug_pubnames + 0x00000672 0x54 ARM RAM Debug/LPC230x.o + .debug_pubnames + 0x000006c6 0x46 ARM RAM Debug/VIC_PL192.o + .debug_pubnames + 0x0000070c 0x1d /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_pubnames + 0x00000729 0x1e /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_pubnames + 0x00000747 0x21 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_aranges 0x00000000 0x188 + .debug_aranges + 0x00000000 0x20 ARM RAM Debug/easyweb.o + .debug_aranges + 0x00000020 0x20 ARM RAM Debug/EMAC.o + .debug_aranges + 0x00000040 0x20 ARM RAM Debug/tcpip.o + .debug_aranges + 0x00000060 0x20 ARM RAM Debug/catch_irqs.o + .debug_aranges + 0x00000080 0x20 ARM RAM Debug/crt0.o + .debug_aranges + 0x000000a0 0x28 ARM RAM Debug/Philips_LPC230X_Startup.o + .debug_aranges + 0x000000c8 0x20 ARM RAM Debug/LPC230x.o + .debug_aranges + 0x000000e8 0x20 ARM RAM Debug/VIC_PL192.o + .debug_aranges + 0x00000108 0x20 ARM RAM Debug/VIC_PL192_irq_handler.o + .debug_aranges + 0x00000128 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_aranges + 0x00000148 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_aranges + 0x00000168 0x20 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_str 0x00000000 0x155 + .debug_str 0x00000000 0x12 ARM RAM Debug/easyweb.o + .debug_str 0x00000012 0x1b ARM RAM Debug/tcpip.o + .debug_str 0x0000002d 0x7 ARM RAM Debug/VIC_PL192.o + .debug_str 0x00000034 0x5b /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_str 0x0000008f 0x51 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + 0x5d (size before relaxing) + .debug_str 0x000000e0 0x75 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + 0x81 (size before relaxing) + +.comment 0x00000000 0xd8 + .comment 0x00000000 0x12 ARM RAM Debug/easyweb.o + .comment 0x00000012 0x12 ARM RAM Debug/EMAC.o + .comment 0x00000024 0x12 ARM RAM Debug/Retarget.o + .comment 0x00000036 0x12 ARM RAM Debug/tcpip.o + .comment 0x00000048 0x12 ARM RAM Debug/catch_irqs.o + .comment 0x0000005a 0x12 ARM RAM Debug/LPC230x.o + .comment 0x0000006c 0x12 ARM RAM Debug/VIC_PL192.o + .comment 0x0000007e 0x12 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .comment 0x00000090 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .comment 0x000000a2 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .comment 0x000000b4 0x12 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .comment 0x000000c6 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) Index: /webserver/example/EasyWEB/ARM RAM Debug/EasyWeb.ld =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/EasyWeb.ld (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/EasyWeb.ld (revision 10) @@ -0,0 +1,219 @@ +MEMORY +{ + UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 + AHB_Peripherals (wx) : ORIGIN = 0xffe00000, LENGTH = 0x00200000 + Battery_RAM (wx) : ORIGIN = 0xe0084000, LENGTH = 0x00000800 + APB_Peripherals (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00200000 + USB_RAM (wx) : ORIGIN = 0x7fd00000, LENGTH = 0x00002000 + Ethernet_RAM (wx) : ORIGIN = 0x7fe00000, LENGTH = 0x00004000 + SRAM (wx) : ORIGIN = 0x40000000, LENGTH = 0x00008000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 +} + + +SECTIONS +{ + __AHB_Peripherals_segment_start__ = 0xffe00000; + __AHB_Peripherals_segment_end__ = 0x00000000; + __Battery_RAM_segment_start__ = 0xe0084000; + __Battery_RAM_segment_end__ = 0xe0084800; + __APB_Peripherals_segment_start__ = 0xe0000000; + __APB_Peripherals_segment_end__ = 0xe0200000; + __USB_RAM_segment_start__ = 0x7fd00000; + __USB_RAM_segment_end__ = 0x7fd02000; + __Ethernet_RAM_segment_start__ = 0x7fe00000; + __Ethernet_RAM_segment_end__ = 0x7fe04000; + __SRAM_segment_start__ = 0x40000000; + __SRAM_segment_end__ = 0x40008000; + __FLASH_segment_start__ = 0x00000000; + __FLASH_segment_end__ = 0x00080000; + + __STACKSIZE__ = 1024; + __STACKSIZE_IRQ__ = 256; + __STACKSIZE_FIQ__ = 256; + __STACKSIZE_SVC__ = 0; + __STACKSIZE_ABT__ = 0; + __STACKSIZE_UND__ = 0; + __HEAPSIZE__ = 1024; + + __vectors_load_start__ = __SRAM_segment_start__; + .vectors __SRAM_segment_start__ : + { + __vectors_start__ = .; + *(.vectors .vectors.*) + } + __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); + + . = ASSERT(__vectors_end__ >= __SRAM_segment_start__ && __vectors_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .vectors is too large to fit in SRAM memory segment"); + + __fast_load_start__ = ALIGN(__vectors_end__ , 4); + .fast ALIGN(__vectors_end__ , 4) : + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + . = ASSERT(__fast_end__ >= __SRAM_segment_start__ && __fast_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .fast is too large to fit in SRAM memory segment"); + + __init_load_start__ = ALIGN(__fast_end__ , 4); + .init ALIGN(__fast_end__ , 4) : + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __SRAM_segment_start__ && __init_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .init is too large to fit in SRAM memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __SRAM_segment_start__ && __text_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .text is too large to fit in SRAM memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __SRAM_segment_start__ && __dtors_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .dtors is too large to fit in SRAM memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __SRAM_segment_start__ && __ctors_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .ctors is too large to fit in SRAM memory segment"); + + __data_load_start__ = ALIGN(__ctors_end__ , 4); + .data ALIGN(__ctors_end__ , 4) : + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + . = ASSERT(__data_end__ >= __SRAM_segment_start__ && __data_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .data is too large to fit in SRAM memory segment"); + + __rodata_load_start__ = ALIGN(__data_end__ , 4); + .rodata ALIGN(__data_end__ , 4) : + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __SRAM_segment_start__ && __rodata_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .rodata is too large to fit in SRAM memory segment"); + + __bss_load_start__ = ALIGN(__rodata_end__ , 4); + .bss ALIGN(__rodata_end__ , 4) (NOLOAD) : + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in SRAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in SRAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in SRAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in SRAM memory segment"); + + __stack_irq_load_start__ = ALIGN(__stack_end__ , 4); + .stack_irq ALIGN(__stack_end__ , 4) (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = ALIGN(MAX(__stack_irq_start__ + __STACKSIZE_IRQ__ , .), 4); + } + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + . = ASSERT(__stack_irq_end__ >= __SRAM_segment_start__ && __stack_irq_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_irq is too large to fit in SRAM memory segment"); + + __stack_fiq_load_start__ = ALIGN(__stack_irq_end__ , 4); + .stack_fiq ALIGN(__stack_irq_end__ , 4) (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = ALIGN(MAX(__stack_fiq_start__ + __STACKSIZE_FIQ__ , .), 4); + } + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + . = ASSERT(__stack_fiq_end__ >= __SRAM_segment_start__ && __stack_fiq_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_fiq is too large to fit in SRAM memory segment"); + + __stack_svc_load_start__ = ALIGN(__stack_fiq_end__ , 4); + .stack_svc ALIGN(__stack_fiq_end__ , 4) (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = ALIGN(MAX(__stack_svc_start__ + __STACKSIZE_SVC__ , .), 4); + } + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + . = ASSERT(__stack_svc_end__ >= __SRAM_segment_start__ && __stack_svc_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_svc is too large to fit in SRAM memory segment"); + + __stack_abt_load_start__ = ALIGN(__stack_svc_end__ , 4); + .stack_abt ALIGN(__stack_svc_end__ , 4) (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = ALIGN(MAX(__stack_abt_start__ + __STACKSIZE_ABT__ , .), 4); + } + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + . = ASSERT(__stack_abt_end__ >= __SRAM_segment_start__ && __stack_abt_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_abt is too large to fit in SRAM memory segment"); + + __stack_und_load_start__ = ALIGN(__stack_abt_end__ , 4); + .stack_und ALIGN(__stack_abt_end__ , 4) (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = ALIGN(MAX(__stack_und_start__ + __STACKSIZE_UND__ , .), 4); + } + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + __SRAM_segment_used_end__ = ALIGN(__stack_abt_end__ , 4) + SIZEOF(.stack_und); + + . = ASSERT(__stack_und_end__ >= __SRAM_segment_start__ && __stack_und_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_und is too large to fit in SRAM memory segment"); + +} + Index: /webserver/example/EasyWEB/ARM RAM Debug/LPC230x.d =================================================================== --- /webserver/example/EasyWEB/ARM RAM Debug/LPC230x.d (revision 10) +++ /webserver/example/EasyWEB/ARM RAM Debug/LPC230x.d (revision 10) @@ -0,0 +1,9 @@ +ARM\ RAM\ Debug/LPC230x.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/LPC230x.c \ + /home/phil/CrossWorks_ARM_1_7/include/ctl_api.h \ + /home/phil/CrossWorks_ARM_1_7/include/libarm.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2000.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2368.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/liblpc2000.h Index: /webserver/example/EasyWEB/LPC23xx.h =================================================================== --- /webserver/example/EasyWEB/LPC23xx.h (revision 10) +++ /webserver/example/EasyWEB/LPC23xx.h (revision 10) @@ -0,0 +1,1131 @@ +/****************************************************************************** + * LPC23xx.h: Header file for NXP LPC23xx/24xx Family Microprocessors + * The header file is the super set of all hardware definition of the + * peripherals for the LPC23xx/24xx family microprocessor. + * + * Copyright(C) 2006, NXP Semiconductor + * All rights reserved. + * + * History + * 2005.10.01 ver 1.00 Prelimnary version, first Release + * +******************************************************************************/ + +#ifndef __LPC23xx_H +#define __LPC23xx_H + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) + +#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) + +/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, +these registers are known as "VICVectPriority(x)". */ +#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) +#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) +#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) +#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) +#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) +#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) +#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) +#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) +#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) +#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) +#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) +#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) +#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) +#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) +#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) +#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) +#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) +#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) +#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) +#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) +#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) +#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) +#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) +#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) +#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) +#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) +#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) +#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) +#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) +#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) +#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) +#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) + + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) + +#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) + + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +// #define APBDIV (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100)) +#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) + +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +are for LPC24xx only. */ +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 + +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 + +/* External Memory Controller (EMC) */ +#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#define TMR2_BASE_ADDR 0xE0070000 +#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#define TMR3_BASE_ADDR 0xE0074000 +#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) + +#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) +#define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24)) +#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0xE0078000 +#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) +#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0xE007C000 +#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) +#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#define I2C2_BASE_ADDR 0xE0080000 +#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) + + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) +#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0xE008C000 +#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0xE0088000 +#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0xFFE04000 +#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) + + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ + +#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) + +/* USB Host and OTG registers are for LPC24xx only */ +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0xFFE0C000 +#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0xFFE0C100 +#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) + +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) + +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Note: below three register name convention is for LPC23xx USB device only, match +with the spec. update in USB Device Section. */ +#define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) +#define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + + +#endif // __LPC23xx_H + Index: /webserver/example/EasyWEB/ARM Flash Release/Retarget.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/Retarget.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/Retarget.d (revision 10) @@ -0,0 +1,2 @@ +ARM\ Flash\ Release/Retarget.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/Retarget.c Index: /webserver/example/EasyWEB/ARM Flash Release/easyweb.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/easyweb.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/easyweb.d (revision 10) @@ -0,0 +1,11 @@ +ARM\ Flash\ Release/easyweb.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/easyweb.c \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdio.h \ + /home/phil/CrossWorks_ARM_1_7/include/string.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/easyweb.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/LPC23xx.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/webpage.h Index: /webserver/example/EasyWEB/ARM Flash Release/tcpip.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/tcpip.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/tcpip.d (revision 10) @@ -0,0 +1,6 @@ +ARM\ Flash\ Release/tcpip.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.c \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/include/string.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h LPC23xx.h Index: /webserver/example/EasyWEB/ARM Flash Release/VIC_PL192_irq_handler.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/VIC_PL192_irq_handler.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/VIC_PL192_irq_handler.d (revision 10) @@ -0,0 +1,3 @@ +ARM\ Flash\ Release/VIC_PL192_irq_handler.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_PL192_irq_handler.s \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_irq_handler.s Index: /webserver/example/EasyWEB/ARM Flash Release/EMAC.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/EMAC.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/EMAC.d (revision 10) @@ -0,0 +1,4 @@ +ARM\ Flash\ Release/EMAC.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.c \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h LPC23xx.h Index: /webserver/example/EasyWEB/ARM Flash Release/Philips_LPC230X_Startup.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/Philips_LPC230X_Startup.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/Philips_LPC230X_Startup.d (revision 10) @@ -0,0 +1,4 @@ +ARM\ Flash\ Release/Philips_LPC230X_Startup.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/Philips_LPC230X_Startup.s \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2000.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2368.h Index: /webserver/example/EasyWEB/ARM Flash Release/VIC_PL192.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/VIC_PL192.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/VIC_PL192.d (revision 10) @@ -0,0 +1,6 @@ +ARM\ Flash\ Release/VIC_PL192.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_PL192.c \ + /home/phil/CrossWorks_ARM_1_7/include/ctl_api.h \ + /home/phil/CrossWorks_ARM_1_7/include/libarm.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h Index: /webserver/example/EasyWEB/ARM Flash Release/crt0.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/crt0.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/crt0.d (revision 10) @@ -0,0 +1,2 @@ +ARM\ Flash\ Release/crt0.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../source/crt0.s Index: /webserver/example/EasyWEB/ARM Flash Release/EasyWeb.map =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/EasyWeb.map (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/EasyWeb.map (revision 10) @@ -0,0 +1,563 @@ +Archive member included because of file (symbol) + +/home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + ARM Flash Release/LPC230x.o (liblpc2000_lpc23xx_get_cclk) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) (__udivsi3) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + ARM Flash Release/easyweb.o (memcpy) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + ARM Flash Release/tcpip.o (memset) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + ARM Flash Release/tcpip.o (memcmp) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + ARM Flash Release/easyweb.o (sprintf) +/home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) (__vfprintf) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) (strlen) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) (__hex_uc) + +Allocating common symbols +Common symbol size file + +TCPTimer 0x1 ARM Flash Release/easyweb.o +HTTPBytesToSend 0x4 ARM Flash Release/easyweb.o +TCPRxDataCount 0x2 ARM Flash Release/easyweb.o +HTTPStatus 0x1 ARM Flash Release/easyweb.o +TCPTxDataCount 0x2 ARM Flash Release/easyweb.o +RecdFrameIP 0x4 ARM Flash Release/easyweb.o +RemoteMAC 0x6 ARM Flash Release/easyweb.o +TCPStateMachine 0x4 ARM Flash Release/easyweb.o +TCPUNASeqNr 0x4 ARM Flash Release/easyweb.o +TCPLocalPort 0x2 ARM Flash Release/easyweb.o +_RxTCPBuffer 0x100 ARM Flash Release/easyweb.o +TCPFlags 0x1 ARM Flash Release/easyweb.o +RecdFrameMAC 0x6 ARM Flash Release/easyweb.o +RecdIPFrameLength 0x2 ARM Flash Release/easyweb.o +PWebSide 0x4 ARM Flash Release/easyweb.o +RemoteIP 0x4 ARM Flash Release/easyweb.o +LastFrameSent 0x4 ARM Flash Release/easyweb.o +TCPRemotePort 0x2 ARM Flash Release/easyweb.o +TxFrame2Size 0x1 ARM Flash Release/easyweb.o +TCPAckNr 0x4 ARM Flash Release/easyweb.o +TransmitControl 0x1 ARM Flash Release/easyweb.o +TxFrame1Size 0x2 ARM Flash Release/easyweb.o +ISNGenHigh 0x2 ARM Flash Release/easyweb.o +_TxFrame2 0x4a ARM Flash Release/easyweb.o +RecdFrameLength 0x2 ARM Flash Release/easyweb.o +_TxFrame1 0x236 ARM Flash Release/easyweb.o +TCPSeqNr 0x4 ARM Flash Release/easyweb.o +RetryCounter 0x1 ARM Flash Release/easyweb.o +SocketStatus 0x1 ARM Flash Release/easyweb.o + +Memory Configuration + +Name Origin Length Attributes +UNPLACED_SECTIONS 0xffffffff 0x00000000 xw +AHB_Peripherals 0xffe00000 0x00200000 xw +Battery_RAM 0xe0084000 0x00000800 xw +APB_Peripherals 0xe0000000 0x00200000 xw +USB_RAM 0x7fd00000 0x00002000 xw +Ethernet_RAM 0x7fe00000 0x00004000 xw +SRAM 0x40000000 0x00008000 xw +FLASH 0x00000000 0x00080000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + + 0xffe00000 __AHB_Peripherals_segment_start__ = 0xffe00000 + 0x00000000 __AHB_Peripherals_segment_end__ = 0x0 + 0xe0084000 __Battery_RAM_segment_start__ = 0xe0084000 + 0xe0084800 __Battery_RAM_segment_end__ = 0xe0084800 + 0xe0000000 __APB_Peripherals_segment_start__ = 0xe0000000 + 0xe0200000 __APB_Peripherals_segment_end__ = 0xe0200000 + 0x7fd00000 __USB_RAM_segment_start__ = 0x7fd00000 + 0x7fd02000 __USB_RAM_segment_end__ = 0x7fd02000 + 0x7fe00000 __Ethernet_RAM_segment_start__ = 0x7fe00000 + 0x7fe04000 __Ethernet_RAM_segment_end__ = 0x7fe04000 + 0x40000000 __SRAM_segment_start__ = 0x40000000 + 0x40008000 __SRAM_segment_end__ = 0x40008000 + 0x00000000 __FLASH_segment_start__ = 0x0 + 0x00080000 __FLASH_segment_end__ = 0x80000 + 0x00000400 __STACKSIZE__ = 0x400 + 0x00000100 __STACKSIZE_IRQ__ = 0x100 + 0x00000100 __STACKSIZE_FIQ__ = 0x100 + 0x00000000 __STACKSIZE_SVC__ = 0x0 + 0x00000000 __STACKSIZE_ABT__ = 0x0 + 0x00000000 __STACKSIZE_UND__ = 0x0 + 0x00000400 __HEAPSIZE__ = 0x400 + 0x40000000 __vectors_ram_load_start__ = __SRAM_segment_start__ + +.vectors_ram 0x40000000 0x3c + 0x40000000 __vectors_ram_start__ = . + *(.vectors_ram) + 0x4000003c . = ((__vectors_ram_start__ + 0x3c) MAX_K .) + *fill* 0x40000000 0x3c 00 + 0x4000003c __vectors_ram_end__ = (__vectors_ram_start__ + SIZEOF (.vectors_ram)) + 0x00000001 . = ASSERT (((__vectors_ram_end__ >= __SRAM_segment_start__) && (__vectors_ram_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .vectors_ram is too large to fit in SRAM memory segment) + 0x00000000 __vectors_load_start__ = __FLASH_segment_start__ + +.vectors 0x00000000 0x38 + 0x00000000 __vectors_start__ = . + *(.vectors .vectors.*) + .vectors 0x00000000 0x38 ARM Flash Release/Philips_LPC230X_Startup.o + 0x00000000 _vectors + 0x00000038 __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors)) + 0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .vectors is too large to fit in FLASH memory segment) + 0x00000038 __init_load_start__ = (__vectors_end__ ALIGN 0x4) + +.init 0x00000038 0x2e0 + 0x00000038 __init_start__ = . + *(.init .init.*) + *fill* 0x00000038 0x8 00 + .init 0x00000040 0x1d0 ARM Flash Release/crt0.o + 0x00000040 __start + 0x00000040 _start + .init 0x00000210 0x108 ARM Flash Release/Philips_LPC230X_Startup.o + 0x00000210 reset_handler + 0x000002fc undef_handler + 0x00000304 pabort_handler + 0x00000308 dabort_handler + 0x00000300 swi_handler + 0x0000030c fiq_handler + 0x00000318 __init_end__ = (__init_start__ + SIZEOF (.init)) + 0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .init is too large to fit in FLASH memory segment) + 0x00000318 __text_load_start__ = (__init_end__ ALIGN 0x4) + +.text 0x00000318 0x2d28 + 0x00000318 __text_start__ = . + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + .text 0x00000318 0x2f4 ARM Flash Release/easyweb.o + 0x00000374 InsertDynamicValues + 0x00000318 GetAD0Val + 0x00000420 HTTPServer + 0x00000594 main + .glue_7 0x0000060c 0x0 ARM Flash Release/easyweb.o + .glue_7t 0x0000060c 0x0 ARM Flash Release/easyweb.o + .text 0x0000060c 0x610 ARM Flash Release/EMAC.o + 0x00000b80 WriteFrame_EMAC + 0x00000a98 StartReadFrame + 0x00000a00 ReadFrame_EMAC + 0x0000060c write_PHY + 0x00000a18 CopyFromFrame_EMAC + 0x00000650 read_PHY + 0x00000ae0 EndReadFrame + 0x00000bf8 ReadFrameBE_EMAC + 0x00000b78 Rdy4Tx + 0x000006bc rx_descr_init + 0x00000a64 DummyReadFrame_EMAC + 0x00000b98 CopyToFrame_EMAC + 0x00000728 tx_descr_init + 0x0000079c Init_EMAC + 0x00000b10 CheckFrameReceived + 0x00000b30 RequestSend + .glue_7 0x00000c1c 0x0 ARM Flash Release/EMAC.o + .glue_7t 0x00000c1c 0x0 ARM Flash Release/EMAC.o + .text 0x00000c1c 0x0 ARM Flash Release/Retarget.o + .glue_7 0x00000c1c 0x0 ARM Flash Release/Retarget.o + .glue_7t 0x00000c1c 0x0 ARM Flash Release/Retarget.o + .text 0x00000c1c 0x1744 ARM Flash Release/tcpip.o + 0x00001644 TCPHandleRetransmission + 0x00000e54 TCPClockHandler + 0x00000dec TCPStopTimer + 0x00001e7c ProcessEthBroadcastFrame + 0x00001f28 IsBroadcast + 0x00000c1c TCPPassiveOpen + 0x00000ef8 CalcChecksum + 0x00001fa0 DoNetworkStuff + 0x00000c5c TCPClose + 0x00000e04 TCPHandleTimeout + 0x00000d14 TCPTransmitTxBuffer + 0x0000114c PrepareTCP_FRAME + 0x00000ffc PrepareTCP_DATA_FRAME + 0x00001744 ProcessTCPFrame + 0x000013e8 PrepareICMP_ECHO_REPLY + 0x00001308 PrepareARP_ANSWER + 0x00001d34 ProcessEthIAFrame + 0x000016bc TCPActiveOpen + 0x00000dac TCPStartTimeWaitTimer + 0x00000ebc WriteDWBE + 0x00000ea4 WriteWBE + 0x00000ee0 SwapBytes + 0x00000dd8 TCPRestartTimer + 0x00000fb4 SendFrame2 + 0x00000cdc TCPStartRetryTimer + 0x000022e0 TCPLowLevelInit + 0x0000171c ProcessICMPFrame + 0x00000cc4 TCPReleaseRxBuffer + 0x00000fd8 SendFrame1 + 0x00001518 PrepareARP_REQUEST + .glue_7 0x00002360 0x0 ARM Flash Release/tcpip.o + .glue_7t 0x00002360 0x0 ARM Flash Release/tcpip.o + .text 0x00002360 0x0 ARM Flash Release/crt0.o + .glue_7 0x00002360 0x0 ARM Flash Release/crt0.o + .glue_7t 0x00002360 0x0 ARM Flash Release/crt0.o + .text 0x00002360 0x0 ARM Flash Release/Philips_LPC230X_Startup.o + .glue_7 0x00002360 0x0 ARM Flash Release/Philips_LPC230X_Startup.o + .glue_7t 0x00002360 0x0 ARM Flash Release/Philips_LPC230X_Startup.o + .text 0x00002360 0x1a4 ARM Flash Release/LPC230x.o + 0x000023b4 ctl_get_ticks_per_second + 0x00002464 ctl_start_timer + 0x000023bc get_uart_clk + .glue_7 0x00002504 0x0 ARM Flash Release/LPC230x.o + .glue_7t 0x00002504 0x0 ARM Flash Release/LPC230x.o + .text 0x00002504 0xa0 ARM Flash Release/VIC_PL192.o + 0x00002574 ctl_unmask_isr + 0x00002504 ctl_set_isr + 0x0000258c ctl_mask_isr + .glue_7 0x000025a4 0x0 ARM Flash Release/VIC_PL192.o + .glue_7t 0x000025a4 0x0 ARM Flash Release/VIC_PL192.o + .text 0x000025a4 0x44 ARM Flash Release/VIC_PL192_irq_handler.o + 0x000025a4 irq_handler + .glue_7 0x000025e8 0x0 ARM Flash Release/VIC_PL192_irq_handler.o + .glue_7t 0x000025e8 0x0 ARM Flash Release/VIC_PL192_irq_handler.o + .text 0x000025e8 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .text.liblpc2000 + 0x000025e8 0x98 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + 0x000025e8 liblpc2000_lpc23xx_get_cclk + .glue_7 0x00002680 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .glue_7t 0x00002680 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .text 0x00002680 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .text.libc 0x00002680 0x30 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + 0x00002680 __int32_udiv + 0x00002680 __int32_udivmod + 0x00002680 __udivsi3 + .glue_7 0x000026b0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .glue_7t 0x000026b0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .text 0x000026b0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .text.libc 0x000026b0 0x60 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + 0x000026b0 memcpy + .glue_7 0x00002710 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .glue_7t 0x00002710 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .text 0x00002710 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .text.libc 0x00002710 0xa0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + 0x00002710 memset + .glue_7 0x000027b0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .glue_7t 0x000027b0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .text 0x000027b0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .text.libc 0x000027b0 0x68 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + 0x000027b0 memcmp + .glue_7 0x00002818 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .glue_7t 0x00002818 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .text 0x00002818 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .text.libc 0x00002818 0x44 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + 0x00002818 sprintf + .glue_7 0x0000285c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .glue_7t 0x0000285c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .text 0x0000285c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .text.libc 0x0000285c 0x780 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + 0x00002918 __vfprintf + .glue_7 0x00002fdc 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .glue_7t 0x00002fdc 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .text 0x00002fdc 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + *fill* 0x00002fdc 0x4 00 + .text.libc 0x00002fe0 0x60 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + 0x00002fe0 strlen + .glue_7 0x00003040 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .glue_7t 0x00003040 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .text 0x00003040 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .text.libc 0x00003040 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .glue_7 0x00003040 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .glue_7t 0x00003040 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x00003040 __text_end__ = (__text_start__ + SIZEOF (.text)) + 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .text is too large to fit in FLASH memory segment) + 0x00003040 __dtors_load_start__ = (__text_end__ ALIGN 0x4) + +.dtors 0x00003040 0x0 + 0x00003040 __dtors_start__ = . + *(SORT(.dtors.*)) + *(.dtors) + 0x00003040 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) + 0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .dtors is too large to fit in FLASH memory segment) + 0x00003040 __ctors_load_start__ = (__dtors_end__ ALIGN 0x4) + +.ctors 0x00003040 0x0 + 0x00003040 __ctors_start__ = . + *(SORT(.ctors.*)) + *(.ctors) + 0x00003040 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) + 0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .ctors is too large to fit in FLASH memory segment) + 0x00003040 __rodata_load_start__ = (__ctors_end__ ALIGN 0x4) + +.rodata 0x00003040 0x4bc + 0x00003040 __rodata_start__ = . + *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata.str1.4 + 0x00003040 0x4 ARM Flash Release/easyweb.o + .rodata 0x00003044 0x490 ARM Flash Release/easyweb.o + 0x00003044 GetResponse + 0x00003076 SubnetMask + 0x0000307a GatewayIP + 0x00003080 WebSide + 0x00003072 MyIP + .rodata 0x000034d4 0x6 ARM Flash Release/tcpip.o + 0x000034d4 MyMAC + *fill* 0x000034da 0x2 00 + .rodata.libc 0x000034dc 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x000034dc __hex_uc + 0x000034ec __hex_lc + 0x000034fc __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) + 0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .rodata is too large to fit in FLASH memory segment) + 0x000034fc __fast_load_start__ = (__rodata_end__ ALIGN 0x4) + +.fast 0x4000003c 0x0 load address 0x000034fc + 0x4000003c __fast_start__ = . + *(.fast .fast.*) + 0x4000003c __fast_end__ = (__fast_start__ + SIZEOF (.fast)) + 0x000034fc __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast)) + 0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x80000))), error: .fast is too large to fit in FLASH memory segment) + +.fast_run 0x4000003c 0x0 + 0x4000003c __fast_run_start__ = . + 0x4000003c . = ((__fast_run_start__ + SIZEOF (.fast)) MAX_K .) + 0x4000003c __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run)) + 0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .fast_run is too large to fit in SRAM memory segment) + 0x000034fc __data_load_start__ = ((__fast_load_start__ + SIZEOF (.fast)) ALIGN 0x4) + +.data 0x4000003c 0x0 load address 0x000034fc + 0x4000003c __data_start__ = . + *(.data .data.* .gnu.linkonce.d.*) + .data 0x4000003c 0x0 ARM Flash Release/easyweb.o + .data 0x4000003c 0x0 ARM Flash Release/EMAC.o + .data 0x4000003c 0x0 ARM Flash Release/Retarget.o + .data 0x4000003c 0x0 ARM Flash Release/tcpip.o + .data 0x4000003c 0x0 ARM Flash Release/crt0.o + .data 0x4000003c 0x0 ARM Flash Release/Philips_LPC230X_Startup.o + .data 0x4000003c 0x0 ARM Flash Release/LPC230x.o + .data 0x4000003c 0x0 ARM Flash Release/VIC_PL192.o + .data 0x4000003c 0x0 ARM Flash Release/VIC_PL192_irq_handler.o + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x4000003c __data_end__ = (__data_start__ + SIZEOF (.data)) + 0x000034fc __data_load_end__ = (__data_load_start__ + SIZEOF (.data)) + 0x000034fc __FLASH_segment_used_end__ = (((__fast_load_start__ + SIZEOF (.fast)) ALIGN 0x4) + SIZEOF (.data)) + 0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x80000))), error: .data is too large to fit in FLASH memory segment) + +.data_run 0x4000003c 0x0 + 0x4000003c __data_run_start__ = . + 0x4000003c . = ((__data_run_start__ + SIZEOF (.data)) MAX_K .) + 0x4000003c __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run)) + 0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .data_run is too large to fit in SRAM memory segment) + 0x4000003c __bss_load_start__ = (__data_run_end__ ALIGN 0x4) + +.bss 0x4000003c 0x3da + 0x4000003c __bss_start__ = . + *(.bss .bss.* .gnu.linkonce.b.*) + .bss 0x4000003c 0x0 ARM Flash Release/easyweb.o + .bss 0x4000003c 0x8 ARM Flash Release/EMAC.o + .bss 0x40000044 0x0 ARM Flash Release/Retarget.o + .bss 0x40000044 0x0 ARM Flash Release/tcpip.o + .bss 0x40000044 0x0 ARM Flash Release/crt0.o + .bss 0x40000044 0x0 ARM Flash Release/Philips_LPC230X_Startup.o + .bss 0x40000044 0x4 ARM Flash Release/LPC230x.o + .bss 0x40000048 0x0 ARM Flash Release/VIC_PL192.o + .bss 0x40000048 0x0 ARM Flash Release/VIC_PL192_irq_handler.o + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + *(COMMON) + COMMON 0x40000048 0x3ce ARM Flash Release/easyweb.o + 0x40000048 TCPTimer + 0x4000004c HTTPBytesToSend + 0x40000050 TCPRxDataCount + 0x40000052 HTTPStatus + 0x40000054 TCPTxDataCount + 0x40000056 RecdFrameIP + 0x4000005a RemoteMAC + 0x40000060 TCPStateMachine + 0x40000064 TCPUNASeqNr + 0x40000068 TCPLocalPort + 0x4000006a _RxTCPBuffer + 0x4000016a TCPFlags + 0x4000016c RecdFrameMAC + 0x40000172 RecdIPFrameLength + 0x40000174 PWebSide + 0x40000178 RemoteIP + 0x4000017c LastFrameSent + 0x40000180 TCPRemotePort + 0x40000182 TxFrame2Size + 0x40000184 TCPAckNr + 0x40000188 TransmitControl + 0x4000018a TxFrame1Size + 0x4000018c ISNGenHigh + 0x4000018e _TxFrame2 + 0x400001d8 RecdFrameLength + 0x400001da _TxFrame1 + 0x40000410 TCPSeqNr + 0x40000414 RetryCounter + 0x40000415 SocketStatus + 0x40000416 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) + 0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .bss is too large to fit in SRAM memory segment) + 0x40000418 __non_init_load_start__ = (__bss_end__ ALIGN 0x4) + +.non_init 0x40000418 0x0 + 0x40000418 __non_init_start__ = . + *(.non_init .non_init.*) + 0x40000418 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) + 0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .non_init is too large to fit in SRAM memory segment) + 0x40000418 __heap_load_start__ = (__non_init_end__ ALIGN 0x4) + +.heap 0x40000418 0x400 + 0x40000418 __heap_start__ = . + *(.heap) + 0x40000818 . = (((__heap_start__ + __HEAPSIZE__) MAX_K .) ALIGN 0x4) + *fill* 0x40000418 0x400 00 + 0x40000818 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) + 0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .heap is too large to fit in SRAM memory segment) + 0x40000818 __stack_load_start__ = (__heap_end__ ALIGN 0x4) + +.stack 0x40000818 0x400 + 0x40000818 __stack_start__ = . + *(.stack) + 0x40000c18 . = (((__stack_start__ + __STACKSIZE__) MAX_K .) ALIGN 0x4) + *fill* 0x40000818 0x400 00 + 0x40000c18 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) + 0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack is too large to fit in SRAM memory segment) + 0x40000c18 __stack_irq_load_start__ = (__stack_end__ ALIGN 0x4) + +.stack_irq 0x40000c18 0x100 + 0x40000c18 __stack_irq_start__ = . + *(.stack_irq) + 0x40000d18 . = (((__stack_irq_start__ + __STACKSIZE_IRQ__) MAX_K .) ALIGN 0x4) + *fill* 0x40000c18 0x100 00 + 0x40000d18 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq)) + 0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_irq is too large to fit in SRAM memory segment) + 0x40000d18 __stack_fiq_load_start__ = (__stack_irq_end__ ALIGN 0x4) + +.stack_fiq 0x40000d18 0x100 + 0x40000d18 __stack_fiq_start__ = . + *(.stack_fiq) + 0x40000e18 . = (((__stack_fiq_start__ + __STACKSIZE_FIQ__) MAX_K .) ALIGN 0x4) + *fill* 0x40000d18 0x100 00 + 0x40000e18 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq)) + 0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_fiq is too large to fit in SRAM memory segment) + 0x40000e18 __stack_svc_load_start__ = (__stack_fiq_end__ ALIGN 0x4) + +.stack_svc 0x40000e18 0x0 + 0x40000e18 __stack_svc_start__ = . + *(.stack_svc) + 0x40000e1c . = (((__stack_svc_start__ + __STACKSIZE_SVC__) MAX_K .) ALIGN 0x4) + 0x40000e18 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc)) + 0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_svc is too large to fit in SRAM memory segment) + 0x40000e18 __stack_abt_load_start__ = (__stack_svc_end__ ALIGN 0x4) + +.stack_abt 0x40000e18 0x0 + 0x40000e18 __stack_abt_start__ = . + *(.stack_abt) + 0x40000e1c . = (((__stack_abt_start__ + __STACKSIZE_ABT__) MAX_K .) ALIGN 0x4) + 0x40000e18 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt)) + 0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_abt is too large to fit in SRAM memory segment) + 0x40000e18 __stack_und_load_start__ = (__stack_abt_end__ ALIGN 0x4) + +.stack_und 0x40000e18 0x0 + 0x40000e18 __stack_und_start__ = . + *(.stack_und) + 0x40000e1c . = (((__stack_und_start__ + __STACKSIZE_UND__) MAX_K .) ALIGN 0x4) + 0x40000e18 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und)) + 0x40000e18 __SRAM_segment_used_end__ = ((__stack_abt_end__ ALIGN 0x4) + SIZEOF (.stack_und)) + 0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_und is too large to fit in SRAM memory segment) +START GROUP +LOAD ARM Flash Release/easyweb.o +LOAD ARM Flash Release/EMAC.o +LOAD ARM Flash Release/Retarget.o +LOAD ARM Flash Release/tcpip.o +LOAD ARM Flash Release/crt0.o +LOAD ARM Flash Release/Philips_LPC230X_Startup.o +LOAD ARM Flash Release/LPC230x.o +LOAD ARM Flash Release/VIC_PL192.o +LOAD ARM Flash Release/VIC_PL192_irq_handler.o +LOAD /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libm_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libcpp_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libdebugio_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_targetio_impl_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfscanf_long_v4t_a_le.a +END GROUP +OUTPUT(ARM Flash Release/EasyWeb.elf elf32-littlearm) + +.comment 0x00000000 0xc6 + .comment 0x00000000 0x12 ARM Flash Release/easyweb.o + .comment 0x00000012 0x12 ARM Flash Release/EMAC.o + .comment 0x00000024 0x12 ARM Flash Release/Retarget.o + .comment 0x00000036 0x12 ARM Flash Release/tcpip.o + .comment 0x00000048 0x12 ARM Flash Release/LPC230x.o + .comment 0x0000005a 0x12 ARM Flash Release/VIC_PL192.o + .comment 0x0000006c 0x12 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .comment 0x0000007e 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .comment 0x00000090 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .comment 0x000000a2 0x12 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .comment 0x000000b4 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_frame 0x00000000 0x188 + .debug_frame 0x00000000 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .debug_frame 0x00000020 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .debug_frame 0x00000040 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .debug_frame 0x00000060 0x2c /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_frame 0x0000008c 0x40 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_frame 0x000000cc 0x9c /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_frame 0x00000168 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + +.debug_abbrev 0x00000000 0x7b + .debug_abbrev 0x00000000 0x23 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_abbrev 0x00000023 0x23 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_abbrev 0x00000046 0x34 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_abbrev 0x0000007a 0x1 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_info 0x00000000 0xcf + .debug_info 0x00000000 0x32 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_info 0x00000032 0x32 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_info 0x00000064 0x6b /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_info 0x000000cf 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_line 0x00000000 0x15a + .debug_line 0x00000000 0x68 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_line 0x00000068 0x69 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_line 0x000000d1 0x6c /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_line 0x0000013d 0x1d /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_loc 0x00000000 0xde + .debug_loc 0x00000000 0x1f /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_loc 0x0000001f 0x37 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_loc 0x00000056 0x88 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_pubnames + 0x00000000 0x5c + .debug_pubnames + 0x00000000 0x1d /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_pubnames + 0x0000001d 0x1e /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_pubnames + 0x0000003b 0x21 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_aranges 0x00000000 0x60 + .debug_aranges + 0x00000000 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_aranges + 0x00000020 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_aranges + 0x00000040 0x20 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_str 0x00000000 0x121 + .debug_str 0x00000000 0x5b /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_str 0x0000005b 0x51 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + 0x5d (size before relaxing) + .debug_str 0x000000ac 0x75 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + 0x81 (size before relaxing) Index: /webserver/example/EasyWEB/ARM Flash Release/EasyWeb.ld =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/EasyWeb.ld (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/EasyWeb.ld (revision 10) @@ -0,0 +1,254 @@ +MEMORY +{ + UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 + AHB_Peripherals (wx) : ORIGIN = 0xffe00000, LENGTH = 0x00200000 + Battery_RAM (wx) : ORIGIN = 0xe0084000, LENGTH = 0x00000800 + APB_Peripherals (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00200000 + USB_RAM (wx) : ORIGIN = 0x7fd00000, LENGTH = 0x00002000 + Ethernet_RAM (wx) : ORIGIN = 0x7fe00000, LENGTH = 0x00004000 + SRAM (wx) : ORIGIN = 0x40000000, LENGTH = 0x00008000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 +} + + +SECTIONS +{ + __AHB_Peripherals_segment_start__ = 0xffe00000; + __AHB_Peripherals_segment_end__ = 0x00000000; + __Battery_RAM_segment_start__ = 0xe0084000; + __Battery_RAM_segment_end__ = 0xe0084800; + __APB_Peripherals_segment_start__ = 0xe0000000; + __APB_Peripherals_segment_end__ = 0xe0200000; + __USB_RAM_segment_start__ = 0x7fd00000; + __USB_RAM_segment_end__ = 0x7fd02000; + __Ethernet_RAM_segment_start__ = 0x7fe00000; + __Ethernet_RAM_segment_end__ = 0x7fe04000; + __SRAM_segment_start__ = 0x40000000; + __SRAM_segment_end__ = 0x40008000; + __FLASH_segment_start__ = 0x00000000; + __FLASH_segment_end__ = 0x00080000; + + __STACKSIZE__ = 1024; + __STACKSIZE_IRQ__ = 256; + __STACKSIZE_FIQ__ = 256; + __STACKSIZE_SVC__ = 0; + __STACKSIZE_ABT__ = 0; + __STACKSIZE_UND__ = 0; + __HEAPSIZE__ = 1024; + + __vectors_ram_load_start__ = __SRAM_segment_start__; + .vectors_ram __SRAM_segment_start__ (NOLOAD) : + { + __vectors_ram_start__ = .; + *(.vectors_ram) + . = MAX(__vectors_ram_start__ + 0x3C , .); + } + __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram); + + . = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .vectors_ram is too large to fit in SRAM memory segment"); + + __vectors_load_start__ = __FLASH_segment_start__; + .vectors __FLASH_segment_start__ : + { + __vectors_start__ = .; + *(.vectors .vectors.*) + } + __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); + + . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); + + __init_load_start__ = ALIGN(__vectors_end__ , 4); + .init ALIGN(__vectors_end__ , 4) : + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); + + __rodata_load_start__ = ALIGN(__ctors_end__ , 4); + .rodata ALIGN(__ctors_end__ , 4) : + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + .fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); + + .fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + . = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in SRAM memory segment"); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + . = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in SRAM memory segment"); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in SRAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in SRAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in SRAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in SRAM memory segment"); + + __stack_irq_load_start__ = ALIGN(__stack_end__ , 4); + .stack_irq ALIGN(__stack_end__ , 4) (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = ALIGN(MAX(__stack_irq_start__ + __STACKSIZE_IRQ__ , .), 4); + } + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + . = ASSERT(__stack_irq_end__ >= __SRAM_segment_start__ && __stack_irq_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_irq is too large to fit in SRAM memory segment"); + + __stack_fiq_load_start__ = ALIGN(__stack_irq_end__ , 4); + .stack_fiq ALIGN(__stack_irq_end__ , 4) (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = ALIGN(MAX(__stack_fiq_start__ + __STACKSIZE_FIQ__ , .), 4); + } + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + . = ASSERT(__stack_fiq_end__ >= __SRAM_segment_start__ && __stack_fiq_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_fiq is too large to fit in SRAM memory segment"); + + __stack_svc_load_start__ = ALIGN(__stack_fiq_end__ , 4); + .stack_svc ALIGN(__stack_fiq_end__ , 4) (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = ALIGN(MAX(__stack_svc_start__ + __STACKSIZE_SVC__ , .), 4); + } + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + . = ASSERT(__stack_svc_end__ >= __SRAM_segment_start__ && __stack_svc_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_svc is too large to fit in SRAM memory segment"); + + __stack_abt_load_start__ = ALIGN(__stack_svc_end__ , 4); + .stack_abt ALIGN(__stack_svc_end__ , 4) (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = ALIGN(MAX(__stack_abt_start__ + __STACKSIZE_ABT__ , .), 4); + } + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + . = ASSERT(__stack_abt_end__ >= __SRAM_segment_start__ && __stack_abt_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_abt is too large to fit in SRAM memory segment"); + + __stack_und_load_start__ = ALIGN(__stack_abt_end__ , 4); + .stack_und ALIGN(__stack_abt_end__ , 4) (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = ALIGN(MAX(__stack_und_start__ + __STACKSIZE_UND__ , .), 4); + } + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + __SRAM_segment_used_end__ = ALIGN(__stack_abt_end__ , 4) + SIZEOF(.stack_und); + + . = ASSERT(__stack_und_end__ >= __SRAM_segment_start__ && __stack_und_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_und is too large to fit in SRAM memory segment"); + +} + Index: /webserver/example/EasyWEB/ARM Flash Release/LPC230x.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Release/LPC230x.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Release/LPC230x.d (revision 10) @@ -0,0 +1,9 @@ +ARM\ Flash\ Release/LPC230x.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/LPC230x.c \ + /home/phil/CrossWorks_ARM_1_7/include/ctl_api.h \ + /home/phil/CrossWorks_ARM_1_7/include/libarm.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2000.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2368.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/liblpc2000.h Index: /webserver/example/EasyWEB/Retarget.c =================================================================== --- /webserver/example/EasyWEB/Retarget.c (revision 9) +++ /webserver/example/EasyWEB/Retarget.c (revision 10) @@ -9,4 +9,5 @@ /******************************************************************************/ +#if 0 #include @@ -20,2 +21,5 @@ label: goto label; /* endless loop */ } + + +#endif Index: /webserver/example/EasyWEB/EasyWeb.hzp =================================================================== --- /webserver/example/EasyWEB/EasyWeb.hzp (revision 10) +++ /webserver/example/EasyWEB/EasyWeb.hzp (revision 10) @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /webserver/example/EasyWEB/tcpip.c =================================================================== --- /webserver/example/EasyWEB/tcpip.c (revision 9) +++ /webserver/example/EasyWEB/tcpip.c (revision 10) @@ -33,6 +33,6 @@ T0MCR = 3; // Interrupt and Reset on MR0 T0TCR = 1; // Timer0 Enable - VICVectAddr4 = (unsigned int)TCPClockHandler; // set interrupt vector in 4 - VICIntEnable = 0x00000010; // Enable Timer0 Interrupt + //VICVectAddr4 = (unsigned int)&TCPClockHandler; // set interrupt vector in 4 + //VICIntEnable = 0x00000010; // Enable Timer0 Interrupt Init_EMAC(); @@ -913,5 +913,7 @@ // function executed every 0.210s by the CPU. used for the // inital sequence number generator (ISN) and the TCP-timer -void TCPClockHandler(void) __irq // Keil: interrupt service routine for timer 0 +//void TCPClockHandler(void) __irq // Keil: interrupt service routine for timer 0 + +void TCPClockHandler(void) { ISNGenHigh++; // upper 16 bits of initial sequence number Index: /webserver/example/EasyWEB/catch_irqs.cpp =================================================================== --- /webserver/example/EasyWEB/catch_irqs.cpp (revision 10) +++ /webserver/example/EasyWEB/catch_irqs.cpp (revision 10) @@ -0,0 +1,24 @@ +void irq_handler (void) +{ +//debug_printf("Bad Interrupt - IRQ Handler\n"); +while (1) ; +} + +void fiq_handler (void) +{ +//debug_printf("Bad Interrupt - FIQ Handler\n"); +while (1) ; +} + +void swi_handler (void) +{ +//debug_printf("Bad Interrupt - SW Interrupt Handler\n"); +while (1) ; +} + +void undef_handler (void) +{ +//debug_printf("Bad Interrupt - Undefined Handler\n"); +while (1) ; +} + Index: /webserver/example/EasyWEB/EasyWeb.hzs =================================================================== --- /webserver/example/EasyWEB/EasyWeb.hzs (revision 10) +++ /webserver/example/EasyWEB/EasyWeb.hzs (revision 10) @@ -0,0 +1,103 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: /webserver/example/EasyWEB/ARM Flash Debug/Retarget.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/Retarget.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/Retarget.d (revision 10) @@ -0,0 +1,2 @@ +ARM\ Flash\ Debug/Retarget.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/Retarget.c Index: /webserver/example/EasyWEB/ARM Flash Debug/easyweb.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/easyweb.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/easyweb.d (revision 10) @@ -0,0 +1,11 @@ +ARM\ Flash\ Debug/easyweb.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/easyweb.c \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdio.h \ + /home/phil/CrossWorks_ARM_1_7/include/string.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/easyweb.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/LPC23xx.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/webpage.h Index: /webserver/example/EasyWEB/ARM Flash Debug/tcpip.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/tcpip.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/tcpip.d (revision 10) @@ -0,0 +1,6 @@ +ARM\ Flash\ Debug/tcpip.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.c \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/include/string.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h LPC23xx.h Index: /webserver/example/EasyWEB/ARM Flash Debug/VIC_PL192_irq_handler.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/VIC_PL192_irq_handler.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/VIC_PL192_irq_handler.d (revision 10) @@ -0,0 +1,3 @@ +ARM\ Flash\ Debug/VIC_PL192_irq_handler.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_PL192_irq_handler.s \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_irq_handler.s Index: /webserver/example/EasyWEB/ARM Flash Debug/EMAC.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/EMAC.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/EMAC.d (revision 10) @@ -0,0 +1,4 @@ +ARM\ Flash\ Debug/EMAC.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.c \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/EMAC.h \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/tcpip.h LPC23xx.h Index: /webserver/example/EasyWEB/ARM Flash Debug/Philips_LPC230X_Startup.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/Philips_LPC230X_Startup.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/Philips_LPC230X_Startup.d (revision 10) @@ -0,0 +1,4 @@ +ARM\ Flash\ Debug/Philips_LPC230X_Startup.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/Philips_LPC230X_Startup.s \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2000.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2368.h Index: /webserver/example/EasyWEB/ARM Flash Debug/VIC_PL192.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/VIC_PL192.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/VIC_PL192.d (revision 10) @@ -0,0 +1,6 @@ +ARM\ Flash\ Debug/VIC_PL192.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/VIC_PL192.c \ + /home/phil/CrossWorks_ARM_1_7/include/ctl_api.h \ + /home/phil/CrossWorks_ARM_1_7/include/libarm.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h Index: /webserver/example/EasyWEB/ARM Flash Debug/crt0.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/crt0.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/crt0.d (revision 10) @@ -0,0 +1,2 @@ +ARM\ Flash\ Debug/crt0.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../source/crt0.s Index: /webserver/example/EasyWEB/ARM Flash Debug/EasyWeb.map =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/EasyWeb.map (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/EasyWeb.map (revision 10) @@ -0,0 +1,628 @@ +Archive member included because of file (symbol) + +/home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + ARM Flash Debug/LPC230x.o (liblpc2000_lpc23xx_get_cclk) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) (__udivsi3) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + ARM Flash Debug/easyweb.o (memcpy) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + ARM Flash Debug/tcpip.o (memset) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + ARM Flash Debug/tcpip.o (memcmp) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + ARM Flash Debug/easyweb.o (sprintf) +/home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) (__vfprintf) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) (strlen) +/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) (__hex_uc) + +Allocating common symbols +Common symbol size file + +TCPTimer 0x1 ARM Flash Debug/easyweb.o +HTTPBytesToSend 0x4 ARM Flash Debug/easyweb.o +TCPRxDataCount 0x2 ARM Flash Debug/easyweb.o +HTTPStatus 0x1 ARM Flash Debug/easyweb.o +TCPTxDataCount 0x2 ARM Flash Debug/easyweb.o +RecdFrameIP 0x4 ARM Flash Debug/easyweb.o +RemoteMAC 0x6 ARM Flash Debug/easyweb.o +TCPStateMachine 0x4 ARM Flash Debug/easyweb.o +TCPUNASeqNr 0x4 ARM Flash Debug/easyweb.o +TCPLocalPort 0x2 ARM Flash Debug/easyweb.o +_RxTCPBuffer 0x100 ARM Flash Debug/easyweb.o +TCPFlags 0x1 ARM Flash Debug/easyweb.o +RecdFrameMAC 0x6 ARM Flash Debug/easyweb.o +RecdIPFrameLength 0x2 ARM Flash Debug/easyweb.o +PWebSide 0x4 ARM Flash Debug/easyweb.o +RemoteIP 0x4 ARM Flash Debug/easyweb.o +LastFrameSent 0x4 ARM Flash Debug/easyweb.o +TCPRemotePort 0x2 ARM Flash Debug/easyweb.o +TxFrame2Size 0x1 ARM Flash Debug/easyweb.o +TCPAckNr 0x4 ARM Flash Debug/easyweb.o +TransmitControl 0x1 ARM Flash Debug/easyweb.o +TxFrame1Size 0x2 ARM Flash Debug/easyweb.o +ISNGenHigh 0x2 ARM Flash Debug/easyweb.o +_TxFrame2 0x4a ARM Flash Debug/easyweb.o +RecdFrameLength 0x2 ARM Flash Debug/easyweb.o +_TxFrame1 0x236 ARM Flash Debug/easyweb.o +TCPSeqNr 0x4 ARM Flash Debug/easyweb.o +RetryCounter 0x1 ARM Flash Debug/easyweb.o +SocketStatus 0x1 ARM Flash Debug/easyweb.o + +Memory Configuration + +Name Origin Length Attributes +UNPLACED_SECTIONS 0xffffffff 0x00000000 xw +AHB_Peripherals 0xffe00000 0x00200000 xw +Battery_RAM 0xe0084000 0x00000800 xw +APB_Peripherals 0xe0000000 0x00200000 xw +USB_RAM 0x7fd00000 0x00002000 xw +Ethernet_RAM 0x7fe00000 0x00004000 xw +SRAM 0x40000000 0x00008000 xw +FLASH 0x00000000 0x00080000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + + 0xffe00000 __AHB_Peripherals_segment_start__ = 0xffe00000 + 0x00000000 __AHB_Peripherals_segment_end__ = 0x0 + 0xe0084000 __Battery_RAM_segment_start__ = 0xe0084000 + 0xe0084800 __Battery_RAM_segment_end__ = 0xe0084800 + 0xe0000000 __APB_Peripherals_segment_start__ = 0xe0000000 + 0xe0200000 __APB_Peripherals_segment_end__ = 0xe0200000 + 0x7fd00000 __USB_RAM_segment_start__ = 0x7fd00000 + 0x7fd02000 __USB_RAM_segment_end__ = 0x7fd02000 + 0x7fe00000 __Ethernet_RAM_segment_start__ = 0x7fe00000 + 0x7fe04000 __Ethernet_RAM_segment_end__ = 0x7fe04000 + 0x40000000 __SRAM_segment_start__ = 0x40000000 + 0x40008000 __SRAM_segment_end__ = 0x40008000 + 0x00000000 __FLASH_segment_start__ = 0x0 + 0x00080000 __FLASH_segment_end__ = 0x80000 + 0x00000400 __STACKSIZE__ = 0x400 + 0x00000100 __STACKSIZE_IRQ__ = 0x100 + 0x00000100 __STACKSIZE_FIQ__ = 0x100 + 0x00000000 __STACKSIZE_SVC__ = 0x0 + 0x00000000 __STACKSIZE_ABT__ = 0x0 + 0x00000000 __STACKSIZE_UND__ = 0x0 + 0x00000400 __HEAPSIZE__ = 0x400 + 0x40000000 __vectors_ram_load_start__ = __SRAM_segment_start__ + +.vectors_ram 0x40000000 0x3c + 0x40000000 __vectors_ram_start__ = . + *(.vectors_ram) + 0x4000003c . = ((__vectors_ram_start__ + 0x3c) MAX_K .) + *fill* 0x40000000 0x3c 00 + 0x4000003c __vectors_ram_end__ = (__vectors_ram_start__ + SIZEOF (.vectors_ram)) + 0x00000001 . = ASSERT (((__vectors_ram_end__ >= __SRAM_segment_start__) && (__vectors_ram_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .vectors_ram is too large to fit in SRAM memory segment) + 0x00000000 __vectors_load_start__ = __FLASH_segment_start__ + +.vectors 0x00000000 0x38 + 0x00000000 __vectors_start__ = . + *(.vectors .vectors.*) + .vectors 0x00000000 0x38 ARM Flash Debug/Philips_LPC230X_Startup.o + 0x00000000 _vectors + 0x00000038 __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors)) + 0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .vectors is too large to fit in FLASH memory segment) + 0x00000038 __init_load_start__ = (__vectors_end__ ALIGN 0x4) + +.init 0x00000038 0x2e0 + 0x00000038 __init_start__ = . + *(.init .init.*) + *fill* 0x00000038 0x8 00 + .init 0x00000040 0x1d0 ARM Flash Debug/crt0.o + 0x00000040 __start + 0x00000040 _start + .init 0x00000210 0x108 ARM Flash Debug/Philips_LPC230X_Startup.o + 0x00000210 reset_handler + 0x000002fc undef_handler + 0x00000304 pabort_handler + 0x00000308 dabort_handler + 0x00000300 swi_handler + 0x0000030c fiq_handler + 0x00000318 __init_end__ = (__init_start__ + SIZEOF (.init)) + 0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .init is too large to fit in FLASH memory segment) + 0x00000318 __text_load_start__ = (__init_end__ ALIGN 0x4) + +.text 0x00000318 0x4438 + 0x00000318 __text_start__ = . + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + .text 0x00000318 0x474 ARM Flash Debug/easyweb.o + 0x00000688 InsertDynamicValues + 0x000005ec GetAD0Val + 0x000003cc HTTPServer + 0x00000318 main + .glue_7 0x0000078c 0x0 ARM Flash Debug/easyweb.o + .glue_7t 0x0000078c 0x0 ARM Flash Debug/easyweb.o + .text 0x0000078c 0xcac ARM Flash Debug/EMAC.o + 0x0000132c WriteFrame_EMAC + 0x00001128 StartReadFrame + 0x00000fc4 ReadFrame_EMAC + 0x0000078c write_PHY + 0x00001058 CopyFromFrame_EMAC + 0x0000082c read_PHY + 0x000011c4 EndReadFrame + 0x00001004 ReadFrameBE_EMAC + 0x0000130c Rdy4Tx + 0x000008fc rx_descr_init + 0x000010e4 DummyReadFrame_EMAC + 0x00001370 CopyToFrame_EMAC + 0x00000a2c tx_descr_init + 0x00000b48 Init_EMAC + 0x00001228 CheckFrameReceived + 0x00001288 RequestSend + .glue_7 0x00001438 0x0 ARM Flash Debug/EMAC.o + .glue_7t 0x00001438 0x0 ARM Flash Debug/EMAC.o + .text 0x00001438 0x0 ARM Flash Debug/Retarget.o + .glue_7 0x00001438 0x0 ARM Flash Debug/Retarget.o + .glue_7t 0x00001438 0x0 ARM Flash Debug/Retarget.o + .text 0x00001438 0x2410 ARM Flash Debug/tcpip.o + 0x00003514 TCPHandleRetransmission + 0x0000360c TCPClockHandler + 0x000034e4 TCPStopTimer + 0x00001c28 ProcessEthBroadcastFrame + 0x00001784 IsBroadcast + 0x000014f4 TCPPassiveOpen + 0x00003268 CalcChecksum + 0x00001830 DoNetworkStuff + 0x000015e8 TCPClose + 0x000035a0 TCPHandleTimeout + 0x000016a4 TCPTransmitTxBuffer + 0x00002c6c PrepareTCP_FRAME + 0x00002ff8 PrepareTCP_DATA_FRAME + 0x00001f0c ProcessTCPFrame + 0x00002a34 PrepareICMP_ECHO_REPLY + 0x000028e4 PrepareARP_ANSWER + 0x00001d04 ProcessEthIAFrame + 0x00001554 TCPActiveOpen + 0x00003464 TCPStartTimeWaitTimer + 0x00003754 WriteDWBE + 0x000036f4 WriteWBE + 0x000037e8 SwapBytes + 0x000034bc TCPRestartTimer + 0x000036bc SendFrame2 + 0x000033f8 TCPStartRetryTimer + 0x00001438 TCPLowLevelInit + 0x00001ec0 ProcessICMPFrame + 0x00001674 TCPReleaseRxBuffer + 0x00003684 SendFrame1 + 0x00002704 PrepareARP_REQUEST + .glue_7 0x00003848 0x0 ARM Flash Debug/tcpip.o + .glue_7t 0x00003848 0x0 ARM Flash Debug/tcpip.o + .text 0x00003848 0x0 ARM Flash Debug/crt0.o + .glue_7 0x00003848 0x0 ARM Flash Debug/crt0.o + .glue_7t 0x00003848 0x0 ARM Flash Debug/crt0.o + .text 0x00003848 0x0 ARM Flash Debug/Philips_LPC230X_Startup.o + .glue_7 0x00003848 0x0 ARM Flash Debug/Philips_LPC230X_Startup.o + .glue_7t 0x00003848 0x0 ARM Flash Debug/Philips_LPC230X_Startup.o + .text 0x00003848 0x2fc ARM Flash Debug/LPC230x.o + 0x00003b24 ctl_get_ticks_per_second + 0x00003a2c ctl_start_timer + 0x000038d0 get_uart_clk + .glue_7 0x00003b44 0x0 ARM Flash Debug/LPC230x.o + .glue_7t 0x00003b44 0x0 ARM Flash Debug/LPC230x.o + .text 0x00003b44 0x168 ARM Flash Debug/VIC_PL192.o + 0x00003c2c ctl_unmask_isr + 0x00003b44 ctl_set_isr + 0x00003c6c ctl_mask_isr + .glue_7 0x00003cac 0x0 ARM Flash Debug/VIC_PL192.o + .glue_7t 0x00003cac 0x0 ARM Flash Debug/VIC_PL192.o + .text 0x00003cac 0x44 ARM Flash Debug/VIC_PL192_irq_handler.o + 0x00003cac irq_handler + .glue_7 0x00003cf0 0x0 ARM Flash Debug/VIC_PL192_irq_handler.o + .glue_7t 0x00003cf0 0x0 ARM Flash Debug/VIC_PL192_irq_handler.o + .text 0x00003cf0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .text.liblpc2000 + 0x00003cf0 0x98 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + 0x00003cf0 liblpc2000_lpc23xx_get_cclk + .glue_7 0x00003d88 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .glue_7t 0x00003d88 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .text 0x00003d88 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + *fill* 0x00003d88 0x8 00 + .text.libc 0x00003d90 0x30 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + 0x00003d90 __int32_udiv + 0x00003d90 __int32_udivmod + 0x00003d90 __udivsi3 + .glue_7 0x00003dc0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .glue_7t 0x00003dc0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .text 0x00003dc0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .text.libc 0x00003dc0 0x60 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + 0x00003dc0 memcpy + .glue_7 0x00003e20 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .glue_7t 0x00003e20 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .text 0x00003e20 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .text.libc 0x00003e20 0xa0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + 0x00003e20 memset + .glue_7 0x00003ec0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .glue_7t 0x00003ec0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .text 0x00003ec0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .text.libc 0x00003ec0 0x68 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + 0x00003ec0 memcmp + .glue_7 0x00003f28 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .glue_7t 0x00003f28 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .text 0x00003f28 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .text.libc 0x00003f28 0x44 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + 0x00003f28 sprintf + .glue_7 0x00003f6c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .glue_7t 0x00003f6c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .text 0x00003f6c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .text.libc 0x00003f6c 0x780 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + 0x00004028 __vfprintf + .glue_7 0x000046ec 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .glue_7t 0x000046ec 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .text 0x000046ec 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + *fill* 0x000046ec 0x4 00 + .text.libc 0x000046f0 0x60 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + 0x000046f0 strlen + .glue_7 0x00004750 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .glue_7t 0x00004750 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .text 0x00004750 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .text.libc 0x00004750 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .glue_7 0x00004750 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + .glue_7t 0x00004750 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x00004750 __text_end__ = (__text_start__ + SIZEOF (.text)) + 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .text is too large to fit in FLASH memory segment) + 0x00004750 __dtors_load_start__ = (__text_end__ ALIGN 0x4) + +.dtors 0x00004750 0x0 + 0x00004750 __dtors_start__ = . + *(SORT(.dtors.*)) + *(.dtors) + 0x00004750 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) + 0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .dtors is too large to fit in FLASH memory segment) + 0x00004750 __ctors_load_start__ = (__dtors_end__ ALIGN 0x4) + +.ctors 0x00004750 0x0 + 0x00004750 __ctors_start__ = . + *(SORT(.ctors.*)) + *(.ctors) + 0x00004750 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) + 0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .ctors is too large to fit in FLASH memory segment) + 0x00004750 __rodata_load_start__ = (__ctors_end__ ALIGN 0x4) + +.rodata 0x00004750 0x4bc + 0x00004750 __rodata_start__ = . + *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata 0x00004750 0x494 ARM Flash Debug/easyweb.o + 0x00004750 GetResponse + 0x00004782 SubnetMask + 0x00004786 GatewayIP + 0x0000478c WebSide + 0x0000477e MyIP + .rodata 0x00004be4 0x6 ARM Flash Debug/tcpip.o + 0x00004be4 MyMAC + *fill* 0x00004bea 0x2 00 + .rodata.libc 0x00004bec 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x00004bec __hex_uc + 0x00004bfc __hex_lc + 0x00004c0c __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) + 0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x80000))), error: .rodata is too large to fit in FLASH memory segment) + 0x00004c0c __fast_load_start__ = (__rodata_end__ ALIGN 0x4) + +.fast 0x4000003c 0x0 load address 0x00004c0c + 0x4000003c __fast_start__ = . + *(.fast .fast.*) + 0x4000003c __fast_end__ = (__fast_start__ + SIZEOF (.fast)) + 0x00004c0c __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast)) + 0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x80000))), error: .fast is too large to fit in FLASH memory segment) + +.fast_run 0x4000003c 0x0 + 0x4000003c __fast_run_start__ = . + 0x4000003c . = ((__fast_run_start__ + SIZEOF (.fast)) MAX_K .) + 0x4000003c __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run)) + 0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .fast_run is too large to fit in SRAM memory segment) + 0x00004c0c __data_load_start__ = ((__fast_load_start__ + SIZEOF (.fast)) ALIGN 0x4) + +.data 0x4000003c 0x0 load address 0x00004c0c + 0x4000003c __data_start__ = . + *(.data .data.* .gnu.linkonce.d.*) + .data 0x4000003c 0x0 ARM Flash Debug/easyweb.o + .data 0x4000003c 0x0 ARM Flash Debug/EMAC.o + .data 0x4000003c 0x0 ARM Flash Debug/Retarget.o + .data 0x4000003c 0x0 ARM Flash Debug/tcpip.o + .data 0x4000003c 0x0 ARM Flash Debug/crt0.o + .data 0x4000003c 0x0 ARM Flash Debug/Philips_LPC230X_Startup.o + .data 0x4000003c 0x0 ARM Flash Debug/LPC230x.o + .data 0x4000003c 0x0 ARM Flash Debug/VIC_PL192.o + .data 0x4000003c 0x0 ARM Flash Debug/VIC_PL192_irq_handler.o + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .data 0x4000003c 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + 0x4000003c __data_end__ = (__data_start__ + SIZEOF (.data)) + 0x00004c0c __data_load_end__ = (__data_load_start__ + SIZEOF (.data)) + 0x00004c0c __FLASH_segment_used_end__ = (((__fast_load_start__ + SIZEOF (.fast)) ALIGN 0x4) + SIZEOF (.data)) + 0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x80000))), error: .data is too large to fit in FLASH memory segment) + +.data_run 0x4000003c 0x0 + 0x4000003c __data_run_start__ = . + 0x4000003c . = ((__data_run_start__ + SIZEOF (.data)) MAX_K .) + 0x4000003c __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run)) + 0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .data_run is too large to fit in SRAM memory segment) + 0x4000003c __bss_load_start__ = (__data_run_end__ ALIGN 0x4) + +.bss 0x4000003c 0x3da + 0x4000003c __bss_start__ = . + *(.bss .bss.* .gnu.linkonce.b.*) + .bss 0x4000003c 0x0 ARM Flash Debug/easyweb.o + .bss 0x4000003c 0x8 ARM Flash Debug/EMAC.o + .bss 0x40000044 0x0 ARM Flash Debug/Retarget.o + .bss 0x40000044 0x0 ARM Flash Debug/tcpip.o + .bss 0x40000044 0x0 ARM Flash Debug/crt0.o + .bss 0x40000044 0x0 ARM Flash Debug/Philips_LPC230X_Startup.o + .bss 0x40000044 0x4 ARM Flash Debug/LPC230x.o + .bss 0x40000048 0x0 ARM Flash Debug/VIC_PL192.o + .bss 0x40000048 0x0 ARM Flash Debug/VIC_PL192_irq_handler.o + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + .bss 0x40000048 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + *(COMMON) + COMMON 0x40000048 0x3ce ARM Flash Debug/easyweb.o + 0x40000048 TCPTimer + 0x4000004c HTTPBytesToSend + 0x40000050 TCPRxDataCount + 0x40000052 HTTPStatus + 0x40000054 TCPTxDataCount + 0x40000056 RecdFrameIP + 0x4000005a RemoteMAC + 0x40000060 TCPStateMachine + 0x40000064 TCPUNASeqNr + 0x40000068 TCPLocalPort + 0x4000006a _RxTCPBuffer + 0x4000016a TCPFlags + 0x4000016c RecdFrameMAC + 0x40000172 RecdIPFrameLength + 0x40000174 PWebSide + 0x40000178 RemoteIP + 0x4000017c LastFrameSent + 0x40000180 TCPRemotePort + 0x40000182 TxFrame2Size + 0x40000184 TCPAckNr + 0x40000188 TransmitControl + 0x4000018a TxFrame1Size + 0x4000018c ISNGenHigh + 0x4000018e _TxFrame2 + 0x400001d8 RecdFrameLength + 0x400001da _TxFrame1 + 0x40000410 TCPSeqNr + 0x40000414 RetryCounter + 0x40000415 SocketStatus + 0x40000416 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) + 0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .bss is too large to fit in SRAM memory segment) + 0x40000418 __non_init_load_start__ = (__bss_end__ ALIGN 0x4) + +.non_init 0x40000418 0x0 + 0x40000418 __non_init_start__ = . + *(.non_init .non_init.*) + 0x40000418 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) + 0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .non_init is too large to fit in SRAM memory segment) + 0x40000418 __heap_load_start__ = (__non_init_end__ ALIGN 0x4) + +.heap 0x40000418 0x400 + 0x40000418 __heap_start__ = . + *(.heap) + 0x40000818 . = (((__heap_start__ + __HEAPSIZE__) MAX_K .) ALIGN 0x4) + *fill* 0x40000418 0x400 00 + 0x40000818 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) + 0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .heap is too large to fit in SRAM memory segment) + 0x40000818 __stack_load_start__ = (__heap_end__ ALIGN 0x4) + +.stack 0x40000818 0x400 + 0x40000818 __stack_start__ = . + *(.stack) + 0x40000c18 . = (((__stack_start__ + __STACKSIZE__) MAX_K .) ALIGN 0x4) + *fill* 0x40000818 0x400 00 + 0x40000c18 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) + 0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack is too large to fit in SRAM memory segment) + 0x40000c18 __stack_irq_load_start__ = (__stack_end__ ALIGN 0x4) + +.stack_irq 0x40000c18 0x100 + 0x40000c18 __stack_irq_start__ = . + *(.stack_irq) + 0x40000d18 . = (((__stack_irq_start__ + __STACKSIZE_IRQ__) MAX_K .) ALIGN 0x4) + *fill* 0x40000c18 0x100 00 + 0x40000d18 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq)) + 0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_irq is too large to fit in SRAM memory segment) + 0x40000d18 __stack_fiq_load_start__ = (__stack_irq_end__ ALIGN 0x4) + +.stack_fiq 0x40000d18 0x100 + 0x40000d18 __stack_fiq_start__ = . + *(.stack_fiq) + 0x40000e18 . = (((__stack_fiq_start__ + __STACKSIZE_FIQ__) MAX_K .) ALIGN 0x4) + *fill* 0x40000d18 0x100 00 + 0x40000e18 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq)) + 0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_fiq is too large to fit in SRAM memory segment) + 0x40000e18 __stack_svc_load_start__ = (__stack_fiq_end__ ALIGN 0x4) + +.stack_svc 0x40000e18 0x0 + 0x40000e18 __stack_svc_start__ = . + *(.stack_svc) + 0x40000e1c . = (((__stack_svc_start__ + __STACKSIZE_SVC__) MAX_K .) ALIGN 0x4) + 0x40000e18 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc)) + 0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_svc is too large to fit in SRAM memory segment) + 0x40000e18 __stack_abt_load_start__ = (__stack_svc_end__ ALIGN 0x4) + +.stack_abt 0x40000e18 0x0 + 0x40000e18 __stack_abt_start__ = . + *(.stack_abt) + 0x40000e1c . = (((__stack_abt_start__ + __STACKSIZE_ABT__) MAX_K .) ALIGN 0x4) + 0x40000e18 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt)) + 0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_abt is too large to fit in SRAM memory segment) + 0x40000e18 __stack_und_load_start__ = (__stack_abt_end__ ALIGN 0x4) + +.stack_und 0x40000e18 0x0 + 0x40000e18 __stack_und_start__ = . + *(.stack_und) + 0x40000e1c . = (((__stack_und_start__ + __STACKSIZE_UND__) MAX_K .) ALIGN 0x4) + 0x40000e18 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und)) + 0x40000e18 __SRAM_segment_used_end__ = ((__stack_abt_end__ ALIGN 0x4) + SIZEOF (.stack_und)) + 0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_und is too large to fit in SRAM memory segment) +START GROUP +LOAD ARM Flash Debug/easyweb.o +LOAD ARM Flash Debug/EMAC.o +LOAD ARM Flash Debug/Retarget.o +LOAD ARM Flash Debug/tcpip.o +LOAD ARM Flash Debug/crt0.o +LOAD ARM Flash Debug/Philips_LPC230X_Startup.o +LOAD ARM Flash Debug/LPC230x.o +LOAD ARM Flash Debug/VIC_PL192.o +LOAD ARM Flash Debug/VIC_PL192_irq_handler.o +LOAD /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libm_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libcpp_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libdebugio_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_targetio_impl_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a +LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfscanf_long_v4t_a_le.a +END GROUP +OUTPUT(ARM Flash Debug/EasyWeb.elf elf32-littlearm) + +.debug_abbrev 0x00000000 0x55d + .debug_abbrev 0x00000000 0xec ARM Flash Debug/easyweb.o + .debug_abbrev 0x000000ec 0xf7 ARM Flash Debug/EMAC.o + .debug_abbrev 0x000001e3 0x1 ARM Flash Debug/Retarget.o + .debug_abbrev 0x000001e4 0x15f ARM Flash Debug/tcpip.o + .debug_abbrev 0x00000343 0x14 ARM Flash Debug/crt0.o + .debug_abbrev 0x00000357 0x10 ARM Flash Debug/Philips_LPC230X_Startup.o + .debug_abbrev 0x00000367 0xc9 ARM Flash Debug/LPC230x.o + .debug_abbrev 0x00000430 0x9e ARM Flash Debug/VIC_PL192.o + .debug_abbrev 0x000004ce 0x14 ARM Flash Debug/VIC_PL192_irq_handler.o + .debug_abbrev 0x000004e2 0x23 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_abbrev 0x00000505 0x23 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_abbrev 0x00000528 0x34 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_abbrev 0x0000055c 0x1 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_info 0x00000000 0x1dde + .debug_info 0x00000000 0x6e8 ARM Flash Debug/easyweb.o + .debug_info 0x000006e8 0x4bf ARM Flash Debug/EMAC.o + .debug_info 0x00000ba7 0x0 ARM Flash Debug/Retarget.o + .debug_info 0x00000ba7 0xad0 ARM Flash Debug/tcpip.o + .debug_info 0x00001677 0x98 ARM Flash Debug/crt0.o + .debug_info 0x0000170f 0xb4 ARM Flash Debug/Philips_LPC230X_Startup.o + .debug_info 0x000017c3 0x1ff ARM Flash Debug/LPC230x.o + .debug_info 0x000019c2 0x299 ARM Flash Debug/VIC_PL192.o + .debug_info 0x00001c5b 0xb4 ARM Flash Debug/VIC_PL192_irq_handler.o + .debug_info 0x00001d0f 0x32 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_info 0x00001d41 0x32 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_info 0x00001d73 0x6b /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_info 0x00001dde 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_line 0x00000000 0x9f8 + .debug_line 0x00000000 0xd4 ARM Flash Debug/easyweb.o + .debug_line 0x000000d4 0x116 ARM Flash Debug/EMAC.o + .debug_line 0x000001ea 0x1d ARM Flash Debug/Retarget.o + .debug_line 0x00000207 0x281 ARM Flash Debug/tcpip.o + .debug_line 0x00000488 0xd2 ARM Flash Debug/crt0.o + .debug_line 0x0000055a 0xf1 ARM Flash Debug/Philips_LPC230X_Startup.o + .debug_line 0x0000064b 0xe5 ARM Flash Debug/LPC230x.o + .debug_line 0x00000730 0xcf ARM Flash Debug/VIC_PL192.o + .debug_line 0x000007ff 0x9f ARM Flash Debug/VIC_PL192_irq_handler.o + .debug_line 0x0000089e 0x68 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_line 0x00000906 0x69 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_line 0x0000096f 0x6c /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_line 0x000009db 0x1d /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) + +.debug_frame 0x00000000 0xbd4 + .debug_frame 0x00000000 0xc0 ARM Flash Debug/easyweb.o + .debug_frame 0x000000c0 0x2d0 ARM Flash Debug/EMAC.o + .debug_frame 0x00000390 0x53c ARM Flash Debug/tcpip.o + .debug_frame 0x000008cc 0xec ARM Flash Debug/LPC230x.o + .debug_frame 0x000009b8 0x94 ARM Flash Debug/VIC_PL192.o + .debug_frame 0x00000a4c 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__int32_udivmod.o) + .debug_frame 0x00000a6c 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcpy.o) + .debug_frame 0x00000a8c 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memset.o) + .debug_frame 0x00000aac 0x2c /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_frame 0x00000ad8 0x40 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_frame 0x00000b18 0x9c /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .debug_frame 0x00000bb4 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(strlen.o) + +.debug_loc 0x00000000 0xa62 + .debug_loc 0x00000000 0xa8 ARM Flash Debug/easyweb.o + .debug_loc 0x000000a8 0x2a0 ARM Flash Debug/EMAC.o + .debug_loc 0x00000348 0x4ec ARM Flash Debug/tcpip.o + .debug_loc 0x00000834 0xd2 ARM Flash Debug/LPC230x.o + .debug_loc 0x00000906 0x7e ARM Flash Debug/VIC_PL192.o + .debug_loc 0x00000984 0x1f /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_loc 0x000009a3 0x37 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_loc 0x000009da 0x88 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_pubnames + 0x00000000 0x714 + .debug_pubnames + 0x00000000 0x26f ARM Flash Debug/easyweb.o + .debug_pubnames + 0x0000026f 0x135 ARM Flash Debug/EMAC.o + .debug_pubnames + 0x000003a4 0x27a ARM Flash Debug/tcpip.o + .debug_pubnames + 0x0000061e 0x54 ARM Flash Debug/LPC230x.o + .debug_pubnames + 0x00000672 0x46 ARM Flash Debug/VIC_PL192.o + .debug_pubnames + 0x000006b8 0x1d /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_pubnames + 0x000006d5 0x1e /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_pubnames + 0x000006f3 0x21 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_aranges 0x00000000 0x168 + .debug_aranges + 0x00000000 0x20 ARM Flash Debug/easyweb.o + .debug_aranges + 0x00000020 0x20 ARM Flash Debug/EMAC.o + .debug_aranges + 0x00000040 0x20 ARM Flash Debug/tcpip.o + .debug_aranges + 0x00000060 0x20 ARM Flash Debug/crt0.o + .debug_aranges + 0x00000080 0x28 ARM Flash Debug/Philips_LPC230X_Startup.o + .debug_aranges + 0x000000a8 0x20 ARM Flash Debug/LPC230x.o + .debug_aranges + 0x000000c8 0x20 ARM Flash Debug/VIC_PL192.o + .debug_aranges + 0x000000e8 0x20 ARM Flash Debug/VIC_PL192_irq_handler.o + .debug_aranges + 0x00000108 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_aranges + 0x00000128 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .debug_aranges + 0x00000148 0x20 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + +.debug_str 0x00000000 0x155 + .debug_str 0x00000000 0x12 ARM Flash Debug/easyweb.o + .debug_str 0x00000012 0x1b ARM Flash Debug/tcpip.o + .debug_str 0x0000002d 0x7 ARM Flash Debug/VIC_PL192.o + .debug_str 0x00000034 0x5b /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .debug_str 0x0000008f 0x51 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + 0x5d (size before relaxing) + .debug_str 0x000000e0 0x75 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + 0x81 (size before relaxing) + +.comment 0x00000000 0xc6 + .comment 0x00000000 0x12 ARM Flash Debug/easyweb.o + .comment 0x00000012 0x12 ARM Flash Debug/EMAC.o + .comment 0x00000024 0x12 ARM Flash Debug/Retarget.o + .comment 0x00000036 0x12 ARM Flash Debug/tcpip.o + .comment 0x00000048 0x12 ARM Flash Debug/LPC230x.o + .comment 0x0000005a 0x12 ARM Flash Debug/VIC_PL192.o + .comment 0x0000006c 0x12 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le.a(liblpc2000_lpc23xx_get_cclk.o) + .comment 0x0000007e 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(memcmp.o) + .comment 0x00000090 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(sprintf.o) + .comment 0x000000a2 0x12 /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le.a(__vfprintf_long.o) + .comment 0x000000b4 0x12 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le.a(__hex_lc_uc.o) Index: /webserver/example/EasyWEB/ARM Flash Debug/EasyWeb.ld =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/EasyWeb.ld (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/EasyWeb.ld (revision 10) @@ -0,0 +1,254 @@ +MEMORY +{ + UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 + AHB_Peripherals (wx) : ORIGIN = 0xffe00000, LENGTH = 0x00200000 + Battery_RAM (wx) : ORIGIN = 0xe0084000, LENGTH = 0x00000800 + APB_Peripherals (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00200000 + USB_RAM (wx) : ORIGIN = 0x7fd00000, LENGTH = 0x00002000 + Ethernet_RAM (wx) : ORIGIN = 0x7fe00000, LENGTH = 0x00004000 + SRAM (wx) : ORIGIN = 0x40000000, LENGTH = 0x00008000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 +} + + +SECTIONS +{ + __AHB_Peripherals_segment_start__ = 0xffe00000; + __AHB_Peripherals_segment_end__ = 0x00000000; + __Battery_RAM_segment_start__ = 0xe0084000; + __Battery_RAM_segment_end__ = 0xe0084800; + __APB_Peripherals_segment_start__ = 0xe0000000; + __APB_Peripherals_segment_end__ = 0xe0200000; + __USB_RAM_segment_start__ = 0x7fd00000; + __USB_RAM_segment_end__ = 0x7fd02000; + __Ethernet_RAM_segment_start__ = 0x7fe00000; + __Ethernet_RAM_segment_end__ = 0x7fe04000; + __SRAM_segment_start__ = 0x40000000; + __SRAM_segment_end__ = 0x40008000; + __FLASH_segment_start__ = 0x00000000; + __FLASH_segment_end__ = 0x00080000; + + __STACKSIZE__ = 1024; + __STACKSIZE_IRQ__ = 256; + __STACKSIZE_FIQ__ = 256; + __STACKSIZE_SVC__ = 0; + __STACKSIZE_ABT__ = 0; + __STACKSIZE_UND__ = 0; + __HEAPSIZE__ = 1024; + + __vectors_ram_load_start__ = __SRAM_segment_start__; + .vectors_ram __SRAM_segment_start__ (NOLOAD) : + { + __vectors_ram_start__ = .; + *(.vectors_ram) + . = MAX(__vectors_ram_start__ + 0x3C , .); + } + __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram); + + . = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .vectors_ram is too large to fit in SRAM memory segment"); + + __vectors_load_start__ = __FLASH_segment_start__; + .vectors __FLASH_segment_start__ : + { + __vectors_start__ = .; + *(.vectors .vectors.*) + } + __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); + + . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); + + __init_load_start__ = ALIGN(__vectors_end__ , 4); + .init ALIGN(__vectors_end__ , 4) : + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); + + __rodata_load_start__ = ALIGN(__ctors_end__ , 4); + .rodata ALIGN(__ctors_end__ , 4) : + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + .fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); + + .fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + . = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in SRAM memory segment"); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + . = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in SRAM memory segment"); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in SRAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in SRAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in SRAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in SRAM memory segment"); + + __stack_irq_load_start__ = ALIGN(__stack_end__ , 4); + .stack_irq ALIGN(__stack_end__ , 4) (NOLOAD) : + { + __stack_irq_start__ = .; + *(.stack_irq) + . = ALIGN(MAX(__stack_irq_start__ + __STACKSIZE_IRQ__ , .), 4); + } + __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); + + . = ASSERT(__stack_irq_end__ >= __SRAM_segment_start__ && __stack_irq_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_irq is too large to fit in SRAM memory segment"); + + __stack_fiq_load_start__ = ALIGN(__stack_irq_end__ , 4); + .stack_fiq ALIGN(__stack_irq_end__ , 4) (NOLOAD) : + { + __stack_fiq_start__ = .; + *(.stack_fiq) + . = ALIGN(MAX(__stack_fiq_start__ + __STACKSIZE_FIQ__ , .), 4); + } + __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); + + . = ASSERT(__stack_fiq_end__ >= __SRAM_segment_start__ && __stack_fiq_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_fiq is too large to fit in SRAM memory segment"); + + __stack_svc_load_start__ = ALIGN(__stack_fiq_end__ , 4); + .stack_svc ALIGN(__stack_fiq_end__ , 4) (NOLOAD) : + { + __stack_svc_start__ = .; + *(.stack_svc) + . = ALIGN(MAX(__stack_svc_start__ + __STACKSIZE_SVC__ , .), 4); + } + __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); + + . = ASSERT(__stack_svc_end__ >= __SRAM_segment_start__ && __stack_svc_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_svc is too large to fit in SRAM memory segment"); + + __stack_abt_load_start__ = ALIGN(__stack_svc_end__ , 4); + .stack_abt ALIGN(__stack_svc_end__ , 4) (NOLOAD) : + { + __stack_abt_start__ = .; + *(.stack_abt) + . = ALIGN(MAX(__stack_abt_start__ + __STACKSIZE_ABT__ , .), 4); + } + __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); + + . = ASSERT(__stack_abt_end__ >= __SRAM_segment_start__ && __stack_abt_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_abt is too large to fit in SRAM memory segment"); + + __stack_und_load_start__ = ALIGN(__stack_abt_end__ , 4); + .stack_und ALIGN(__stack_abt_end__ , 4) (NOLOAD) : + { + __stack_und_start__ = .; + *(.stack_und) + . = ALIGN(MAX(__stack_und_start__ + __STACKSIZE_UND__ , .), 4); + } + __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); + + __SRAM_segment_used_end__ = ALIGN(__stack_abt_end__ , 4) + SIZEOF(.stack_und); + + . = ASSERT(__stack_und_end__ >= __SRAM_segment_start__ && __stack_und_end__ <= (__SRAM_segment_start__ + 0x00008000) , "error: .stack_und is too large to fit in SRAM memory segment"); + +} + Index: /webserver/example/EasyWEB/ARM Flash Debug/LPC230x.d =================================================================== --- /webserver/example/EasyWEB/ARM Flash Debug/LPC230x.d (revision 10) +++ /webserver/example/EasyWEB/ARM Flash Debug/LPC230x.d (revision 10) @@ -0,0 +1,9 @@ +ARM\ Flash\ Debug/LPC230x.o: \ + /home/phil/CrossWorks_ARM_1_7/Projects/EasyWeb/../../targets/Philips_LPC210X/LPC230x.c \ + /home/phil/CrossWorks_ARM_1_7/include/ctl_api.h \ + /home/phil/CrossWorks_ARM_1_7/include/libarm.h \ + /home/phil/CrossWorks_ARM_1_7/include/stdlib.h \ + /home/phil/CrossWorks_ARM_1_7/include/__crossworks.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2000.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/LPC2368.h \ + /home/phil/CrossWorks_ARM_1_7/include/targets/liblpc2000.h Index: /webserver/example/EasyWEB/tcpip.h =================================================================== --- /webserver/example/EasyWEB/tcpip.h (revision 9) +++ /webserver/example/EasyWEB/tcpip.h (revision 10) @@ -18,5 +18,5 @@ #define MYIP_1 192 // our internet protocol (IP) address #define MYIP_2 168 -#define MYIP_3 1 +#define MYIP_3 3 #define MYIP_4 100 @@ -273,5 +273,10 @@ void TCPReleaseRxBuffer(void); // indicate to discard rec'd packet void TCPTransmitTxBuffer(void); // initiate transfer after TxBuffer is filled -void TCPClockHandler(void) __irq; // Keil: interrupt service routine for timer 0 +//void TCPClockHandler(void) __irq; // Keil: interrupt service routine for timer 0 + + +void TCPClockHandler(void) __attribute__ ((interrupt ("IRQ"))); + + // easyWEB-API global vars and flags Index: /webserver/example/EasyWEB/easyweb.c.bak =================================================================== --- /webserver/example/EasyWEB/easyweb.c.bak (revision 10) +++ /webserver/example/EasyWEB/easyweb.c.bak (revision 10) @@ -0,0 +1,156 @@ +/****************************************************************** + ***** ***** + ***** Name: easyweb.c ***** + ***** Ver.: 1.0 ***** + ***** Date: 07/05/2001 ***** + ***** Auth: Andreas Dannenberg ***** + ***** HTWK Leipzig ***** + ***** university of applied sciences ***** + ***** Germany ***** + ***** Func: implements a dynamic HTTP-server by using ***** + ***** the easyWEB-API ***** + ***** ***** + ******************************************************************/ + +#include +#include +#include + +#define extern // Keil: Line added for modular project management + +#include "easyweb.h" +#include "EMAC.h" // Ethernet packet driver +#include "tcpip.h" // easyWEB TCP/IP stack +#include "LPC23xx.h" // Keil: Register definition file for LPC2368 +#include "webpage.h" // webside for our HTTP server (HTML) + + +//void main(void) +void main(void) +{ + TCPLowLevelInit(); + + /* Start of Config ADC */ + PCONP |= (1<<12); // Power-On Clock Control of ADC + PINSEL1 &= 0xFFFF3FFF; // Reset Pin Config P0[23] + PINSEL1 |= 0x00004000; // Config P0[23] = AD0 + /* End of Config ADC */ + + HTTPStatus = 0; // clear HTTP-server's flag register + TCPLocalPort = TCP_PORT_HTTP; // set port we want to listen to + + while (1) // repeat forever + { + if (!(SocketStatus & SOCK_ACTIVE)) TCPPassiveOpen(); // listen for incoming TCP-connection + DoNetworkStuff(); // handle network and easyWEB-stack + // events + HTTPServer(); + } +} + +// This function implements a very simple dynamic HTTP-server. +// It waits until connected, then sends a HTTP-header and the +// HTML-code stored in memory. Before sending, it replaces +// some special strings with dynamic values. +// NOTE: For strings crossing page boundaries, replacing will +// not work. In this case, simply add some extra lines +// (e.g. CR and LFs) to the HTML-code. + +void HTTPServer(void) +{ + if (SocketStatus & SOCK_CONNECTED) // check if somebody has connected to our TCP + { + if (SocketStatus & SOCK_DATA_AVAILABLE) // check if remote TCP sent data + TCPReleaseRxBuffer(); // and throw it away + + if (SocketStatus & SOCK_TX_BUF_RELEASED) // check if buffer is free for TX + { + if (!(HTTPStatus & HTTP_SEND_PAGE)) // init byte-counter and pointer to webside + { // if called the 1st time + HTTPBytesToSend = sizeof(WebSide) - 1; // get HTML length, ignore trailing zero + PWebSide = (unsigned char *)WebSide; // pointer to HTML-code + } + + if (HTTPBytesToSend > MAX_TCP_TX_DATA_SIZE) // transmit a segment of MAX_SIZE + { + if (!(HTTPStatus & HTTP_SEND_PAGE)) // 1st time, include HTTP-header + { + memcpy(TCP_TX_BUF, GetResponse, sizeof(GetResponse) - 1); + memcpy(TCP_TX_BUF + sizeof(GetResponse) - 1, PWebSide, MAX_TCP_TX_DATA_SIZE - sizeof(GetResponse) + 1); + HTTPBytesToSend -= MAX_TCP_TX_DATA_SIZE - sizeof(GetResponse) + 1; + PWebSide += MAX_TCP_TX_DATA_SIZE - sizeof(GetResponse) + 1; + } + else + { + memcpy(TCP_TX_BUF, PWebSide, MAX_TCP_TX_DATA_SIZE); + HTTPBytesToSend -= MAX_TCP_TX_DATA_SIZE; + PWebSide += MAX_TCP_TX_DATA_SIZE; + } + + TCPTxDataCount = MAX_TCP_TX_DATA_SIZE; // bytes to xfer + InsertDynamicValues(); // exchange some strings... + TCPTransmitTxBuffer(); // xfer buffer + } + else if (HTTPBytesToSend) // transmit leftover bytes + { + memcpy(TCP_TX_BUF, PWebSide, HTTPBytesToSend); + TCPTxDataCount = HTTPBytesToSend; // bytes to xfer + InsertDynamicValues(); // exchange some strings... + TCPTransmitTxBuffer(); // send last segment + TCPClose(); // and close connection + HTTPBytesToSend = 0; // all data sent + } + + HTTPStatus |= HTTP_SEND_PAGE; // ok, 1st loop executed + } + } + else + { + HTTPStatus &= ~HTTP_SEND_PAGE; // reset help-flag if not connected + } +} + +unsigned int GetAD0Val(void) +{ + unsigned int val; + + AD0CR = 0x01000001 | 0x002E0400; // Setup A/D: 10-bit AIN0 @ 3MHz + do + { + val = AD0GDR; // Read A/D Data Register + } while ((val & 0x80000000) == 0); // Wait for end of A/D Conversion + AD0CR &= ~0x01000001; // Stop A/D Conversion + val = (val >> 6) & 0x03FF; // Extract AIN0 Value + return(val / 10); // result of A/D process +} + +// searches the TX-buffer for special strings and replaces them +// with dynamic values (AD-converter results) + +void InsertDynamicValues(void) +{ + unsigned char *Key; + char NewKey[5]; + unsigned int i; + + if (TCPTxDataCount < 4) return; // there can't be any special string + + Key = TCP_TX_BUF; + + for (i = 0; i < (TCPTxDataCount - 3); i++) + { + if (*Key == 'A') + if (*(Key + 1) == 'D') + if (*(Key + 3) == '%') + switch (*(Key + 2)) + { + case '0' : // "AD0%"? + { + sprintf(NewKey, "%3u", GetAD0Val()); // insert AD converter value + memcpy(Key, NewKey, 3); // AD0(P0[23]) + break; + } + } + Key++; + } +}