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Timestamp:
06/14/09 08:54:46 (15 years ago)
Author:
phil
Message:

Added Interrupt Enable Commamnd. RAM Debug, Flash Release working (still needs reset after power-on)

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  • webserver/example/EasyWEB/tcpip.c

    r10 r12  
    1818#include <LPC23xx.h>       
    1919 
     20 
     21#define TIMER0_IRQ    4 
     22 
     23 
     24 
    2025const unsigned char MyMAC[6] =   // "M1-M2-M3-M4-M5-M6" 
    2126{ 
    …… 
    3338  T0MCR = 3;                                            // Interrupt and Reset on MR0 
    3439  T0TCR = 1;                                            // Timer0 Enable 
    35   //VICVectAddr4 = (unsigned int)&TCPClockHandler;              // set interrupt vector in 4 
    36   //VICIntEnable = 0x00000010;                                  // Enable Timer0 Interrupt 
    37    
     40  VICVectAddr4 = (unsigned int)TCPClockHandler;         // set interrupt vector in 4 
     41  VICIntEnable = 0x00000010;                            // Enable Timer0 Interrupt 
     42 
     43  __ARMLIB_enableIRQ(); /* Enable IRQs (CrossWorks Compiler) */ 
     44 
     45 
     46 
     47 
    3848  Init_EMAC(); 
    3949  TransmitControl = 0;