Changeset 15
- Timestamp:
- 08/10/09 10:58:19 (15 years ago)
- Files:
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webserver/example/freeRTOS/Demo/ARM7_LPC2368_Rowley/webserver/emac.c
r14 r15 42 42 unsigned int tout; 43 43 44 MA DR = DP83848C_DEF_ADR | PhyReg;45 M WTD = Value;44 MAC_MADR = DP83848C_DEF_ADR | PhyReg; 45 MAC_MWTD = Value; 46 46 47 47 /* Wait utill operation completed */ 48 48 tout = 0; 49 49 for (tout = 0; tout < MII_WR_TOUT; tout++) { 50 if ((M IND & MIND_BUSY) == 0) {50 if ((MAC_MIND & MIND_BUSY) == 0) { 51 51 break; 52 52 } … … 60 60 unsigned int tout; 61 61 62 MA DR = DP83848C_DEF_ADR | PhyReg;63 M CMD = MCMD_READ;62 MAC_MADR = DP83848C_DEF_ADR | PhyReg; 63 MAC_MCMD = MCMD_READ; 64 64 65 65 /* Wait until operation completed */ 66 66 tout = 0; 67 67 for (tout = 0; tout < MII_RD_TOUT; tout++) { 68 if ((M IND & MIND_BUSY) == 0) {68 if ((MAC_MIND & MIND_BUSY) == 0) { 69 69 break; 70 70 } 71 71 } 72 M CMD = 0;73 return (M RDD);72 MAC_MCMD = 0; 73 return (MAC_MRDD); 74 74 } 75 75 … … 88 88 89 89 /* Set EMAC Receive Descriptor Registers. */ 90 RxDescriptor= RX_DESC_BASE;91 RxStatus= RX_STAT_BASE;92 RxDescriptorNumber= NUM_RX_FRAG-1;90 MAC_RXDESCRIPTOR = RX_DESC_BASE; 91 MAC_RXSTATUS = RX_STAT_BASE; 92 MAC_RXDESCRIPTORNUM = NUM_RX_FRAG-1; 93 93 94 94 /* Rx Descriptors Point to 0 */ 95 RxConsumeIndex= 0;95 MAC_RXCONSUMEINDEX = 0; 96 96 } 97 97 … … 108 108 109 109 /* Set EMAC Transmit Descriptor Registers. */ 110 TxDescriptor= TX_DESC_BASE;111 TxStatus= TX_STAT_BASE;112 TxDescriptorNumber= NUM_TX_FRAG-1;110 MAC_TXDESCRIPTOR = TX_DESC_BASE; 111 MAC_TXSTATUS = TX_STAT_BASE; 112 MAC_TXDESCRIPTORNUM = NUM_TX_FRAG-1; 113 113 114 114 /* Tx Descriptors Point to 0 */ 115 TxProduceIndex= 0;115 MAC_TXPRODUCEINDEX = 0; 116 116 } 117 117 … … 137 137 138 138 /* Reset all EMAC internal modules. */ 139 MAC 1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |139 MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | 140 140 MAC1_SIM_RES | MAC1_SOFT_RES; 141 Command= CR_REG_RES | CR_TX_RES | CR_RX_RES;141 MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES; 142 142 143 143 /* A short delay after reset. */ … … 145 145 146 146 /* Initialize MAC control registers. */ 147 MAC 1 = MAC1_PASS_ALL;148 MAC 2 = MAC2_CRC_EN | MAC2_PAD_EN;149 MA XF = ETH_MAX_FLEN;150 CLRT = CLRT_DEF;151 IPGR = IPGR_DEF;147 MAC_MAC1 = MAC1_PASS_ALL; 148 MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; 149 MAC_MAXF = ETH_MAX_FLEN; 150 MAC_CLRT = CLRT_DEF; 151 MAC_IPGR = IPGR_DEF; 152 152 153 153 /* Enable Reduced MII interface. */ 154 Command= CR_RMII | CR_PASS_RUNT_FRM;154 MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM; 155 155 156 156 /* Reset Reduced MII Logic. */ 157 SUPP = SUPP_RES_RMII;158 SUPP = 0;157 MAC_SUPP = SUPP_RES_RMII; 158 MAC_SUPP = 0; 159 159 160 160 /* Put the DP83848C in reset mode */ … … 215 215 if (regv & 0x0004) { 216 216 /* Full duplex is enabled. */ 217 MAC 2 |= MAC2_FULL_DUP;218 Command|= CR_FULL_DUP;219 IPGT = IPGT_FULL_DUP;217 MAC_MAC2 |= MAC2_FULL_DUP; 218 MAC_COMMAND |= CR_FULL_DUP; 219 MAC_IPGT = IPGT_FULL_DUP; 220 220 } 221 221 else { 222 222 /* Half duplex mode. */ 223 IPGT = IPGT_HALF_DUP;223 MAC_IPGT = IPGT_HALF_DUP; 224 224 } 225 225 … … 227 227 if (regv & 0x0002) { 228 228 /* 10MBit mode. */ 229 SUPP = 0;229 MAC_SUPP = 0; 230 230 } 231 231 else { 232 232 /* 100MBit mode. */ 233 SUPP = SUPP_SPEED;233 MAC_SUPP = SUPP_SPEED; 234 234 } 235 235 236 236 /* Set the Ethernet MAC Address registers */ 237 SA0 = (emacETHADDR0 << 8) | emacETHADDR1;238 SA1 = (emacETHADDR2 << 8) | emacETHADDR3;239 SA2 = (emacETHADDR4 << 8) | emacETHADDR5;237 MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1; 238 MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3; 239 MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5; 240 240 241 241 /* Initialize Tx and Rx DMA Descriptors */ … … 244 244 245 245 /* Receive Broadcast and Perfect Match Packets */ 246 RxFilterCtrl= RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;246 MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; 247 247 248 248 /* Create the semaphore used ot wake the uIP task. */ … … 250 250 251 251 /* Reset all interrupts */ 252 IntClear= 0xFFFF;252 MAC_INTCLEAR = 0xFFFF; 253 253 254 254 /* Enable receive and transmit mode of MAC Ethernet core */ 255 Command|= (CR_RX_EN | CR_TX_EN);256 MAC 1 |= MAC1_REC_EN;255 MAC_COMMAND |= (CR_RX_EN | CR_TX_EN); 256 MAC_MAC1 |= MAC1_REC_EN; 257 257 } 258 258 … … 319 319 unsigned int idx; 320 320 321 idx = RxConsumeIndex;321 idx = MAC_RXCONSUMEINDEX; 322 322 RxLen = (RX_STAT_INFO(idx) & RINFO_SIZE) - 3; 323 323 rptr = (unsigned short *)RX_DESC_PACKET(idx); … … 329 329 330 330 /* DMA free packet. */ 331 idx = RxConsumeIndex;331 idx = MAC_RXCONSUMEINDEX; 332 332 333 333 if (++idx == NUM_RX_FRAG) 334 334 idx = 0; 335 335 336 RxConsumeIndex= idx;336 MAC_RXCONSUMEINDEX = idx; 337 337 } 338 338 339 339 unsigned int CheckFrameReceived(void) { // Packet received ? 340 340 341 if ( RxProduceIndex != RxConsumeIndex) // more packets received ?341 if (MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX) // more packets received ? 342 342 return(1); 343 343 else … … 349 349 unsigned int uiLen = 0; 350 350 351 if( RxProduceIndex != RxConsumeIndex)351 if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX ) 352 352 { 353 353 uiLen = StartReadFrame(); … … 365 365 unsigned int idx; 366 366 367 idx = TxProduceIndex;367 idx = MAC_TXPRODUCEINDEX; 368 368 tptr = (unsigned short *)TX_DESC_PACKET(idx); 369 369 } … … 405 405 unsigned int idx; 406 406 407 idx = TxProduceIndex;407 idx = MAC_TXPRODUCEINDEX; 408 408 TX_DESC_CTRL(idx) = FrameSize | TCTRL_LAST; 409 409 if (++idx == NUM_TX_FRAG) idx = 0; 410 TxProduceIndex= idx;411 } 412 410 MAC_TXPRODUCEINDEX = idx; 411 } 412