Archive member included because of file (symbol) /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) ARM RAM Debug/main.o (ctl_task_init) /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o) /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) (ctl_private_init_registers) /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) ARM RAM Debug/LPC230x.o (liblpc2000_lpc23xx_get_cclk) /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) (ctl_global_interrupts_set) /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) (__udivsi3) /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) ARM RAM Debug/main.o (memset) Allocating common symbols Common symbol size file ctl_interrupt_count 0x1 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) new_task_stack 0x108 ARM RAM Debug/main_ctl.o ctl_current_time 0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) ctl_timeslice_period 0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) ctl_task_executing 0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) new_task 0x20 ARM RAM Debug/main_ctl.o main_task 0x20 ARM RAM Debug/main_ctl.o ctl_task_list 0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) Memory Configuration Name Origin Length Attributes UNPLACED_SECTIONS 0xffffffff 0x00000000 xw AHB_Peripherals 0xffe00000 0x00200000 xw Battery_RAM 0xe0084000 0x00000800 xw APB_Peripherals 0xe0000000 0x00200000 xw USB_RAM 0x7fd00000 0x00002000 xw Ethernet_RAM 0x7fe00000 0x00004000 xw SRAM 0x40000000 0x00008000 xw FLASH 0x00000000 0x00080000 xr *default* 0x00000000 0xffffffff Linker script and memory map 0xffe00000 __AHB_Peripherals_segment_start__ = 0xffe00000 0x00000000 __AHB_Peripherals_segment_end__ = 0x0 0xe0084000 __Battery_RAM_segment_start__ = 0xe0084000 0xe0084800 __Battery_RAM_segment_end__ = 0xe0084800 0xe0000000 __APB_Peripherals_segment_start__ = 0xe0000000 0xe0200000 __APB_Peripherals_segment_end__ = 0xe0200000 0x7fd00000 __USB_RAM_segment_start__ = 0x7fd00000 0x7fd02000 __USB_RAM_segment_end__ = 0x7fd02000 0x7fe00000 __Ethernet_RAM_segment_start__ = 0x7fe00000 0x7fe04000 __Ethernet_RAM_segment_end__ = 0x7fe04000 0x40000000 __SRAM_segment_start__ = 0x40000000 0x40008000 __SRAM_segment_end__ = 0x40008000 0x00000000 __FLASH_segment_start__ = 0x0 0x00080000 __FLASH_segment_end__ = 0x80000 0x00000400 __STACKSIZE__ = 0x400 0x00000100 __STACKSIZE_IRQ__ = 0x100 0x00000100 __STACKSIZE_FIQ__ = 0x100 0x00000000 __STACKSIZE_SVC__ = 0x0 0x00000000 __STACKSIZE_ABT__ = 0x0 0x00000000 __STACKSIZE_UND__ = 0x0 0x00000400 __HEAPSIZE__ = 0x400 0x40000000 __vectors_load_start__ = __SRAM_segment_start__ .vectors 0x40000000 0x3c 0x40000000 __vectors_start__ = . *(.vectors .vectors.*) .vectors 0x40000000 0x3c ARM RAM Debug/Philips_LPC230X_Startup.o 0x40000000 _vectors 0x4000003c __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors)) 0x00000001 . = ASSERT (((__vectors_end__ >= __SRAM_segment_start__) && (__vectors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .vectors is too large to fit in SRAM memory segment) 0x4000003c __fast_load_start__ = (__vectors_end__ ALIGN 0x4) .fast 0x4000003c 0x0 0x4000003c __fast_start__ = . *(.fast .fast.*) 0x4000003c __fast_end__ = (__fast_start__ + SIZEOF (.fast)) 0x00000001 . = ASSERT (((__fast_end__ >= __SRAM_segment_start__) && (__fast_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .fast is too large to fit in SRAM memory segment) 0x4000003c __init_load_start__ = (__fast_end__ ALIGN 0x4) .init 0x4000003c 0x2e0 0x4000003c __init_start__ = . *(.init .init.*) *fill* 0x4000003c 0x4 00 .init 0x40000040 0x1d0 ARM RAM Debug/crt0.o 0x40000040 __start 0x40000040 _start .init 0x40000210 0x10c ARM RAM Debug/Philips_LPC230X_Startup.o 0x40000210 reset_handler 0x40000300 undef_handler 0x40000308 pabort_handler 0x4000030c dabort_handler 0x40000304 swi_handler 0x40000310 fiq_handler 0x4000031c __init_end__ = (__init_start__ + SIZEOF (.init)) 0x00000001 . = ASSERT (((__init_end__ >= __SRAM_segment_start__) && (__init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .init is too large to fit in SRAM memory segment) 0x4000031c __text_load_start__ = (__init_end__ ALIGN 0x4) .text 0x4000031c 0x1154 0x4000031c __text_start__ = . *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) .text 0x4000031c 0x44 ARM RAM Debug/main_ctl.o 0x40000348 ctl_handle_error 0x4000031c new_task_code .glue_7 0x40000360 0x0 ARM RAM Debug/main_ctl.o .glue_7t 0x40000360 0x0 ARM RAM Debug/main_ctl.o .text 0x40000360 0x330 ARM RAM Debug/main.o 0x40000360 ConfigBlinky 0x40000454 task1 0x40000500 task2 0x400005ac main 0x40000418 delay .glue_7 0x40000690 0x0 ARM RAM Debug/main.o .glue_7t 0x40000690 0x0 ARM RAM Debug/main.o .text 0x40000690 0x0 ARM RAM Debug/crt0.o .glue_7 0x40000690 0x0 ARM RAM Debug/crt0.o .glue_7t 0x40000690 0x0 ARM RAM Debug/crt0.o .text 0x40000690 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o .glue_7 0x40000690 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o .glue_7t 0x40000690 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o .text 0x40000690 0x2fc ARM RAM Debug/LPC230x.o 0x4000096c ctl_get_ticks_per_second 0x40000874 ctl_start_timer 0x40000718 get_uart_clk .glue_7 0x4000098c 0x0 ARM RAM Debug/LPC230x.o .glue_7t 0x4000098c 0x0 ARM RAM Debug/LPC230x.o .text 0x4000098c 0x168 ARM RAM Debug/VIC_PL192.o 0x40000a74 ctl_unmask_isr 0x4000098c ctl_set_isr 0x40000ab4 ctl_mask_isr .glue_7 0x40000af4 0x0 ARM RAM Debug/VIC_PL192.o .glue_7t 0x40000af4 0x0 ARM RAM Debug/VIC_PL192.o .text 0x40000af4 0x68 ARM RAM Debug/VIC_PL192_irq_handler.o 0x40000af4 irq_handler .glue_7 0x40000b5c 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o .glue_7t 0x40000b5c 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o .text 0x40000b5c 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .text.libctl 0x40000b5c 0x604 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) 0x40000fe8 ctl_task_remove 0x40000eac ctl_private_reschedule 0x400010a8 ctl_task_reschedule 0x40000fa8 ctl_task_set_priority 0x40000bd0 ctl_task_init 0x40000c8c ctl_exit_isr 0x40000f44 ctl_timeout_wait 0x40000e60 ctl_task_die 0x40000c64 ctl_get_current_time 0x400010d8 ctl_task_run 0x40000bf4 ctl_increment_tick_from_isr .glue_7 0x40001160 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .glue_7t 0x40001160 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .text 0x40001160 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o) .text.libctl 0x40001160 0x170 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o) 0x400011c8 ctl_private_switch_context 0x400012b4 ctl_private_isr_return 0x40001238 ctl_private_switch_isr_context 0x40001160 ctl_private_init_registers .glue_7 0x400012d0 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o) .glue_7t 0x400012d0 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o) .text 0x400012d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) .text.liblpc2000 0x400012d0 0x98 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) 0x400012d0 liblpc2000_lpc23xx_get_cclk .glue_7 0x40001368 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) .glue_7t 0x40001368 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) .text 0x40001368 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) *fill* 0x40001368 0x8 00 .text.libc 0x40001370 0x30 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) 0x40001370 ctl_global_interrupts_set 0x40001370 libarm_set_irq .glue_7 0x400013a0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) .glue_7t 0x400013a0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) .text 0x400013a0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) .text.libc 0x400013a0 0x30 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) 0x400013a0 __int32_udiv 0x400013a0 __int32_udivmod 0x400013a0 __udivsi3 .glue_7 0x400013d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) .glue_7t 0x400013d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) .text 0x400013d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) .text.libc 0x400013d0 0xa0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) 0x400013d0 memset .glue_7 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) .glue_7t 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) 0x40001470 __text_end__ = (__text_start__ + SIZEOF (.text)) 0x00000001 . = ASSERT (((__text_end__ >= __SRAM_segment_start__) && (__text_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .text is too large to fit in SRAM memory segment) 0x40001470 __dtors_load_start__ = (__text_end__ ALIGN 0x4) .dtors 0x40001470 0x0 0x40001470 __dtors_start__ = . *(SORT(.dtors.*)) *(.dtors) 0x40001470 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) 0x00000001 . = ASSERT (((__dtors_end__ >= __SRAM_segment_start__) && (__dtors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .dtors is too large to fit in SRAM memory segment) 0x40001470 __ctors_load_start__ = (__dtors_end__ ALIGN 0x4) .ctors 0x40001470 0x0 0x40001470 __ctors_start__ = . *(SORT(.ctors.*)) *(.ctors) 0x40001470 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) 0x00000001 . = ASSERT (((__ctors_end__ >= __SRAM_segment_start__) && (__ctors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .ctors is too large to fit in SRAM memory segment) 0x40001470 __data_load_start__ = (__ctors_end__ ALIGN 0x4) .data 0x40001470 0x0 0x40001470 __data_start__ = . *(.data .data.* .gnu.linkonce.d.*) .data 0x40001470 0x0 ARM RAM Debug/main_ctl.o .data 0x40001470 0x0 ARM RAM Debug/main.o .data 0x40001470 0x0 ARM RAM Debug/crt0.o .data 0x40001470 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o .data 0x40001470 0x0 ARM RAM Debug/LPC230x.o .data 0x40001470 0x0 ARM RAM Debug/VIC_PL192.o .data 0x40001470 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o .data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o) .data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) .data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) .data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) .data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) 0x40001470 __data_end__ = (__data_start__ + SIZEOF (.data)) 0x00000001 . = ASSERT (((__data_end__ >= __SRAM_segment_start__) && (__data_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .data is too large to fit in SRAM memory segment) 0x40001470 __rodata_load_start__ = (__data_end__ ALIGN 0x4) .rodata 0x40001470 0x18 0x40001470 __rodata_start__ = . *(.rodata .rodata.* .gnu.linkonce.r.*) .rodata 0x40001470 0x18 ARM RAM Debug/main.o 0x40001488 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) 0x00000001 . = ASSERT (((__rodata_end__ >= __SRAM_segment_start__) && (__rodata_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .rodata is too large to fit in SRAM memory segment) 0x40001488 __bss_load_start__ = (__rodata_end__ ALIGN 0x4) .bss 0x40001488 0x3c8 0x40001488 __bss_start__ = . *(.bss .bss.* .gnu.linkonce.b.*) .bss 0x40001488 0x0 ARM RAM Debug/main_ctl.o .bss 0x40001488 0x268 ARM RAM Debug/main.o 0x4000148c led_2_state 0x40001488 led_1_state .bss 0x400016f0 0x0 ARM RAM Debug/crt0.o .bss 0x400016f0 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o .bss 0x400016f0 0x4 ARM RAM Debug/LPC230x.o .bss 0x400016f4 0x0 ARM RAM Debug/VIC_PL192.o .bss 0x400016f4 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o .bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o) .bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) .bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) .bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) .bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) *(COMMON) COMMON 0x400016f4 0x148 ARM RAM Debug/main_ctl.o 0x400016f4 new_task_stack 0x400017fc new_task 0x4000181c main_task COMMON 0x4000183c 0x14 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) 0x4000183c ctl_interrupt_count 0x40001840 ctl_current_time 0x40001844 ctl_timeslice_period 0x40001848 ctl_task_executing 0x4000184c ctl_task_list 0x40001850 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) 0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .bss is too large to fit in SRAM memory segment) 0x40001850 __non_init_load_start__ = (__bss_end__ ALIGN 0x4) .non_init 0x40001850 0x0 0x40001850 __non_init_start__ = . *(.non_init .non_init.*) 0x40001850 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) 0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .non_init is too large to fit in SRAM memory segment) 0x40001850 __heap_load_start__ = (__non_init_end__ ALIGN 0x4) .heap 0x40001850 0x400 0x40001850 __heap_start__ = . *(.heap) 0x40001c50 . = (((__heap_start__ + __HEAPSIZE__) MAX_K .) ALIGN 0x4) *fill* 0x40001850 0x400 00 0x40001c50 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) 0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .heap is too large to fit in SRAM memory segment) 0x40001c50 __stack_load_start__ = (__heap_end__ ALIGN 0x4) .stack 0x40001c50 0x400 0x40001c50 __stack_start__ = . *(.stack) 0x40002050 . = (((__stack_start__ + __STACKSIZE__) MAX_K .) ALIGN 0x4) *fill* 0x40001c50 0x400 00 0x40002050 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) 0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack is too large to fit in SRAM memory segment) 0x40002050 __stack_irq_load_start__ = (__stack_end__ ALIGN 0x4) .stack_irq 0x40002050 0x100 0x40002050 __stack_irq_start__ = . *(.stack_irq) 0x40002150 . = (((__stack_irq_start__ + __STACKSIZE_IRQ__) MAX_K .) ALIGN 0x4) *fill* 0x40002050 0x100 00 0x40002150 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq)) 0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_irq is too large to fit in SRAM memory segment) 0x40002150 __stack_fiq_load_start__ = (__stack_irq_end__ ALIGN 0x4) .stack_fiq 0x40002150 0x100 0x40002150 __stack_fiq_start__ = . *(.stack_fiq) 0x40002250 . = (((__stack_fiq_start__ + __STACKSIZE_FIQ__) MAX_K .) ALIGN 0x4) *fill* 0x40002150 0x100 00 0x40002250 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq)) 0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_fiq is too large to fit in SRAM memory segment) 0x40002250 __stack_svc_load_start__ = (__stack_fiq_end__ ALIGN 0x4) .stack_svc 0x40002250 0x0 0x40002250 __stack_svc_start__ = . *(.stack_svc) 0x40002254 . = (((__stack_svc_start__ + __STACKSIZE_SVC__) MAX_K .) ALIGN 0x4) 0x40002250 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc)) 0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_svc is too large to fit in SRAM memory segment) 0x40002250 __stack_abt_load_start__ = (__stack_svc_end__ ALIGN 0x4) .stack_abt 0x40002250 0x0 0x40002250 __stack_abt_start__ = . *(.stack_abt) 0x40002254 . = (((__stack_abt_start__ + __STACKSIZE_ABT__) MAX_K .) ALIGN 0x4) 0x40002250 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt)) 0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_abt is too large to fit in SRAM memory segment) 0x40002250 __stack_und_load_start__ = (__stack_abt_end__ ALIGN 0x4) .stack_und 0x40002250 0x0 0x40002250 __stack_und_start__ = . *(.stack_und) 0x40002254 . = (((__stack_und_start__ + __STACKSIZE_UND__) MAX_K .) ALIGN 0x4) 0x40002250 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und)) 0x40002250 __SRAM_segment_used_end__ = ((__stack_abt_end__ ALIGN 0x4) + SIZEOF (.stack_und)) 0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_und is too large to fit in SRAM memory segment) START GROUP LOAD ARM RAM Debug/main_ctl.o LOAD ARM RAM Debug/main.o LOAD ARM RAM Debug/crt0.o LOAD ARM RAM Debug/Philips_LPC230X_Startup.o LOAD ARM RAM Debug/LPC230x.o LOAD ARM RAM Debug/VIC_PL192.o LOAD ARM RAM Debug/VIC_PL192_irq_handler.o LOAD /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/libm_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/libcpp_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/libdebugio_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_targetio_impl_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le_mt.a LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfscanf_long_v4t_a_le_mt.a END GROUP OUTPUT(ARM RAM Debug/CrossWorks_TaskingLib_Test.elf elf32-littlearm) .debug_abbrev 0x00000000 0x404 .debug_abbrev 0x00000000 0xf8 ARM RAM Debug/main_ctl.o .debug_abbrev 0x000000f8 0x108 ARM RAM Debug/main.o .debug_abbrev 0x00000200 0x14 ARM RAM Debug/crt0.o .debug_abbrev 0x00000214 0x10 ARM RAM Debug/Philips_LPC230X_Startup.o .debug_abbrev 0x00000224 0xc9 ARM RAM Debug/LPC230x.o .debug_abbrev 0x000002ed 0xab ARM RAM Debug/VIC_PL192.o .debug_abbrev 0x00000398 0x14 ARM RAM Debug/VIC_PL192_irq_handler.o .debug_abbrev 0x000003ac 0x58 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .debug_info 0x00000000 0x103e .debug_info 0x00000000 0x362 ARM RAM Debug/main_ctl.o .debug_info 0x00000362 0x3a6 ARM RAM Debug/main.o .debug_info 0x00000708 0xe7 ARM RAM Debug/crt0.o .debug_info 0x000007ef 0x103 ARM RAM Debug/Philips_LPC230X_Startup.o .debug_info 0x000008f2 0x25f ARM RAM Debug/LPC230x.o .debug_info 0x00000b51 0x2ce ARM RAM Debug/VIC_PL192.o .debug_info 0x00000e1f 0x103 ARM RAM Debug/VIC_PL192_irq_handler.o .debug_info 0x00000f22 0x11c /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .debug_line 0x00000000 0x742 .debug_line 0x00000000 0xbd ARM RAM Debug/main_ctl.o .debug_line 0x000000bd 0xe7 ARM RAM Debug/main.o .debug_line 0x000001a4 0x109 ARM RAM Debug/crt0.o .debug_line 0x000002ad 0x129 ARM RAM Debug/Philips_LPC230X_Startup.o .debug_line 0x000003d6 0x120 ARM RAM Debug/LPC230x.o .debug_line 0x000004f6 0x10a ARM RAM Debug/VIC_PL192.o .debug_line 0x00000600 0xdb ARM RAM Debug/VIC_PL192_irq_handler.o .debug_line 0x000006db 0x67 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .debug_frame 0x00000000 0x4b0 .debug_frame 0x00000000 0x68 ARM RAM Debug/main_ctl.o .debug_frame 0x00000068 0xec ARM RAM Debug/main.o .debug_frame 0x00000154 0xec ARM RAM Debug/LPC230x.o .debug_frame 0x00000240 0x94 ARM RAM Debug/VIC_PL192.o .debug_frame 0x000002d4 0x17c /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .debug_frame 0x00000450 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o) .debug_frame 0x00000470 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o) .debug_frame 0x00000490 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o) .debug_loc 0x00000000 0x3cb .debug_loc 0x00000000 0x54 ARM RAM Debug/main_ctl.o .debug_loc 0x00000054 0xd2 ARM RAM Debug/main.o .debug_loc 0x00000126 0xd2 ARM RAM Debug/LPC230x.o .debug_loc 0x000001f8 0x7e ARM RAM Debug/VIC_PL192.o .debug_loc 0x00000276 0x155 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .debug_pubnames 0x00000000 0x271 .debug_pubnames 0x00000000 0x67 ARM RAM Debug/main_ctl.o .debug_pubnames 0x00000067 0x6a ARM RAM Debug/main.o .debug_pubnames 0x000000d1 0x54 ARM RAM Debug/LPC230x.o .debug_pubnames 0x00000125 0x46 ARM RAM Debug/VIC_PL192.o .debug_pubnames 0x0000016b 0x106 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .debug_aranges 0x00000000 0x108 .debug_aranges 0x00000000 0x20 ARM RAM Debug/main_ctl.o .debug_aranges 0x00000020 0x20 ARM RAM Debug/main.o .debug_aranges 0x00000040 0x20 ARM RAM Debug/crt0.o .debug_aranges 0x00000060 0x28 ARM RAM Debug/Philips_LPC230X_Startup.o .debug_aranges 0x00000088 0x20 ARM RAM Debug/LPC230x.o .debug_aranges 0x000000a8 0x20 ARM RAM Debug/VIC_PL192.o .debug_aranges 0x000000c8 0x20 ARM RAM Debug/VIC_PL192_irq_handler.o .debug_aranges 0x000000e8 0x20 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .debug_str 0x00000000 0x17f .debug_str 0x00000000 0x12 ARM RAM Debug/main_ctl.o .debug_str 0x00000012 0x12 ARM RAM Debug/main.o .debug_str 0x00000024 0x7 ARM RAM Debug/VIC_PL192.o .debug_str 0x0000002b 0x154 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .comment 0x00000000 0x6c .comment 0x00000000 0x12 ARM RAM Debug/main_ctl.o .comment 0x00000012 0x12 ARM RAM Debug/main.o .comment 0x00000024 0x12 ARM RAM Debug/LPC230x.o .comment 0x00000036 0x12 ARM RAM Debug/VIC_PL192.o .comment 0x00000048 0x12 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) .comment 0x0000005a 0x12 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)