EMAC.h

Revision 8, 18.9 kB (checked in by phil, 15 years ago)
Added Examples etc. from CD

Line
1	/*----------------------------------------------------------------------------
2	* LPC2378 Ethernet Definitions
3	*----------------------------------------------------------------------------
4	* Name: EMAC.H
5	* Purpose: Philips LPC2378 EMAC hardware definitions
6	*----------------------------------------------------------------------------
7	* Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.
8	---------------------------------------------------------------------------/
9
10	#ifndef __EMAC_H
11	#define __EMAC_H
12
13	#define MYMAC_1 0x00 /* our ethernet (MAC) address */
14	#define MYMAC_2 0x30 /* (MUST be unique in LAN!) */
15	#define MYMAC_3 0x6C
16	#define MYMAC_4 0x00
17	#define MYMAC_5 0x00
18	#define MYMAC_6 0x02
19
20	/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
21	#define NUM_RX_FRAG 4 /* Num.of RX Fragments 41536= 6.0kB /
22	#define NUM_TX_FRAG 3 /* Num.of TX Fragments 31536= 4.6kB /
23	#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
24
25	#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
26
27	/* EMAC variables located in 16K Ethernet SRAM */
28	#define RX_DESC_BASE 0x7FE00000
29	#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
30	#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
31	#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
32	#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
33	#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
34
35	/* RX and TX descriptor and status definitions. */
36	#define RX_DESC_PACKET(i) ((unsigned int )(RX_DESC_BASE + 8*i))
37	#define RX_DESC_CTRL(i) ((unsigned int )(RX_DESC_BASE+4 + 8*i))
38	#define RX_STAT_INFO(i) ((unsigned int )(RX_STAT_BASE + 8*i))
39	#define RX_STAT_HASHCRC(i) ((unsigned int )(RX_STAT_BASE+4 + 8*i))
40	#define TX_DESC_PACKET(i) ((unsigned int )(TX_DESC_BASE + 8*i))
41	#define TX_DESC_CTRL(i) ((unsigned int )(TX_DESC_BASE+4 + 8*i))
42	#define TX_STAT_INFO(i) ((unsigned int )(TX_STAT_BASE + 4*i))
43	#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
44	#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
45
46	/* MAC Configuration Register 1 */
47	#define MAC1_REC_EN 0x00000001 /* Receive Enable */
48	#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
49	#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
50	#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
51	#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
52	#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
53	#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
54	#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
55	#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
56	#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
57	#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
58
59	/* MAC Configuration Register 2 */
60	#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
61	#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
62	#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
63	#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
64	#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
65	#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
66	#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
67	#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
68	#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
69	#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
70	#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
71	#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
72	#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
73
74	/* Back-to-Back Inter-Packet-Gap Register */
75	#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
76	#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
77
78	/* Non Back-to-Back Inter-Packet-Gap Register */
79	#define IPGR_DEF 0x00000012 /* Recommended value */
80
81	/* Collision Window/Retry Register */
82	#define CLRT_DEF 0x0000370F /* Default value */
83
84	/* PHY Support Register */
85	#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
86	#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
87
88	/* Test Register */
89	#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
90	#define TEST_TST_PAUSE 0x00000002 /* Test Pause */
91	#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
92
93	/* MII Management Configuration Register */
94	#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
95	#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
96	#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
97	#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
98
99	/* MII Management Command Register */
100	#define MCMD_READ 0x00000001 /* MII Read */
101	#define MCMD_SCAN 0x00000002 /* MII Scan continuously */
102
103	#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
104	#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
105
106	/* MII Management Address Register */
107	#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
108	#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
109
110	/* MII Management Indicators Register */
111	#define MIND_BUSY 0x00000001 /* MII is Busy */
112	#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
113	#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
114	#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
115
116	/* Command Register */
117	#define CR_RX_EN 0x00000001 /* Enable Receive */
118	#define CR_TX_EN 0x00000002 /* Enable Transmit */
119	#define CR_REG_RES 0x00000008 /* Reset Host Registers */
120	#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
121	#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
122	#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
123	#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
124	#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
125	#define CR_RMII 0x00000200 /* Reduced MII Interface */
126	#define CR_FULL_DUP 0x00000400 /* Full Duplex */
127
128	/* Status Register */
129	#define SR_RX_EN 0x00000001 /* Enable Receive */
130	#define SR_TX_EN 0x00000002 /* Enable Transmit */
131
132	/* Transmit Status Vector 0 Register */
133	#define TSV0_CRC_ERR 0x00000001 /* CRC error */
134	#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
135	#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
136	#define TSV0_DONE 0x00000008 /* Tramsmission Completed */
137	#define TSV0_MCAST 0x00000010 /* Multicast Destination */
138	#define TSV0_BCAST 0x00000020 /* Broadcast Destination */
139	#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
140	#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
141	#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
142	#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
143	#define TSV0_GIANT 0x00000400 /* Giant Frame */
144	#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
145	#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
146	#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
147	#define TSV0_PAUSE 0x20000000 /* Pause Frame */
148	#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
149	#define TSV0_VLAN 0x80000000 /* VLAN Frame */
150
151	/* Transmit Status Vector 1 Register */
152	#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
153	#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
154
155	/* Receive Status Vector Register */
156	#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
157	#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
158	#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
159	#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
160	#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
161	#define RSV_CRC_ERR 0x00100000 /* CRC Error */
162	#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
163	#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
164	#define RSV_REC_OK 0x00800000 /* Frame Received OK */
165	#define RSV_MCAST 0x01000000 /* Multicast Frame */
166	#define RSV_BCAST 0x02000000 /* Broadcast Frame */
167	#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
168	#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
169	#define RSV_PAUSE 0x10000000 /* Pause Frame */
170	#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
171	#define RSV_VLAN 0x40000000 /* VLAN Frame */
172
173	/* Flow Control Counter Register */
174	#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
175	#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
176
177	/* Flow Control Status Register */
178	#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
179
180	/* Receive Filter Control Register */
181	#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
182	#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
183	#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
184	#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
185	#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
186	#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
187	#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
188	#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
189
190	/* Receive Filter WoL Status/Clear Registers */
191	#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
192	#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
193	#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
194	#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
195	#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
196	#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
197	#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
198	#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
199
200	/* Interrupt Status/Enable/Clear/Set Registers */
201	#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
202	#define INT_RX_ERR 0x00000002 /* Receive Error */
203	#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
204	#define INT_RX_DONE 0x00000008 /* Receive Done */
205	#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
206	#define INT_TX_ERR 0x00000020 /* Transmit Error */
207	#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
208	#define INT_TX_DONE 0x00000080 /* Transmit Done */
209	#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
210	#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
211
212	/* Power Down Register */
213	#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
214
215	/* RX Descriptor Control Word */
216	#define RCTRL_SIZE 0x000007FF /* Buffer size mask */
217	#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
218
219	/* RX Status Hash CRC Word */
220	#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
221	#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
222
223	/* RX Status Information Word */
224	#define RINFO_SIZE 0x000007FF /* Data size in bytes */
225	#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
226	#define RINFO_VLAN 0x00080000 /* VLAN Frame */
227	#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
228	#define RINFO_MCAST 0x00200000 /* Multicast Frame */
229	#define RINFO_BCAST 0x00400000 /* Broadcast Frame */
230	#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
231	#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
232	#define RINFO_LEN_ERR 0x02000000 /* Length Error */
233	#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
234	#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
235	#define RINFO_OVERRUN 0x10000000 /* Receive overrun */
236	#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
237	#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
238	#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
239
240	#define RINFO_ERR_MASK (RINFO_FAIL_FILT \| RINFO_CRC_ERR \| RINFO_SYM_ERR \| \
241	RINFO_LEN_ERR \| RINFO_ALIGN_ERR \| RINFO_OVERRUN)
242
243	/* TX Descriptor Control Word */
244	#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
245	#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
246	#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
247	#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
248	#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
249	#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
250	#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
251
252	/* TX Status Information Word */
253	#define TINFO_COL_CNT 0x01E00000 /* Collision Count */
254	#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
255	#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
256	#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
257	#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
258	#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
259	#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
260	#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
261
262	/* ENET Device Revision ID */
263	#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
264
265	/* DP83848C PHY Registers */
266	#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
267	#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
268	#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
269	#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
270	#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
271	#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
272	#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
273	#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
274
275	/* PHY Extended Registers */
276	#define PHY_REG_STS 0x10 /* Status Register */
277	#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
278	#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
279	#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
280	#define PHY_REG_RECR 0x15 /* Receive Error Counter */
281	#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
282	#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
283	#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
284	#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
285	#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
286	#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
287	#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
288
289	#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
290	#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
291	#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
292	#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
293	#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
294
295	#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
296	#define DP83848C_ID 0x20005C90 /* PHY Identifier */
297
298	// prototypes
299	void Init_EMAC(void);
300	unsigned short ReadFrameBE_EMAC(void);
301	void CopyToFrame_EMAC(void *Source, unsigned int Size);
302	void CopyFromFrame_EMAC(void *Dest, unsigned short Size);
303	void DummyReadFrame_EMAC(unsigned short Size);
304	unsigned short StartReadFrame(void);
305	void EndReadFrame(void);
306	unsigned int CheckFrameReceived(void);
307	void RequestSend(unsigned short FrameSize);
308	unsigned int Rdy4Tx(void);
309
310	#endif
311
312	/*----------------------------------------------------------------------------
313	* end of file
314	---------------------------------------------------------------------------/
315

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