CrossWorks_TaskingLib_Test.map

Revision 13, 29.5 kB (checked in by phil, 15 years ago)
Crossworks Lib Example (multiple tasks)

Line
1	Archive member included because of file (symbol)
2
3	/home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
4	ARM RAM Debug/main.o (ctl_task_init)
5	/home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o)
6	/home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) (ctl_private_init_registers)
7	/home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)
8	ARM RAM Debug/LPC230x.o (liblpc2000_lpc23xx_get_cclk)
9	/home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
10	/home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o) (ctl_global_interrupts_set)
11	/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
12	/home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o) (__udivsi3)
13	/home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
14	ARM RAM Debug/main.o (memset)
15
16	Allocating common symbols
17	Common symbol size file
18
19	ctl_interrupt_count
20	0x1 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
21	new_task_stack 0x108 ARM RAM Debug/main_ctl.o
22	ctl_current_time 0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
23	ctl_timeslice_period
24	0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
25	ctl_task_executing 0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
26	new_task 0x20 ARM RAM Debug/main_ctl.o
27	main_task 0x20 ARM RAM Debug/main_ctl.o
28	ctl_task_list 0x4 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
29
30	Memory Configuration
31
32	Name Origin Length Attributes
33	UNPLACED_SECTIONS 0xffffffff 0x00000000 xw
34	AHB_Peripherals 0xffe00000 0x00200000 xw
35	Battery_RAM 0xe0084000 0x00000800 xw
36	APB_Peripherals 0xe0000000 0x00200000 xw
37	USB_RAM 0x7fd00000 0x00002000 xw
38	Ethernet_RAM 0x7fe00000 0x00004000 xw
39	SRAM 0x40000000 0x00008000 xw
40	FLASH 0x00000000 0x00080000 xr
41	default 0x00000000 0xffffffff
42
43	Linker script and memory map
44
45	0xffe00000 __AHB_Peripherals_segment_start__ = 0xffe00000
46	0x00000000 __AHB_Peripherals_segment_end__ = 0x0
47	0xe0084000 __Battery_RAM_segment_start__ = 0xe0084000
48	0xe0084800 __Battery_RAM_segment_end__ = 0xe0084800
49	0xe0000000 __APB_Peripherals_segment_start__ = 0xe0000000
50	0xe0200000 __APB_Peripherals_segment_end__ = 0xe0200000
51	0x7fd00000 __USB_RAM_segment_start__ = 0x7fd00000
52	0x7fd02000 __USB_RAM_segment_end__ = 0x7fd02000
53	0x7fe00000 __Ethernet_RAM_segment_start__ = 0x7fe00000
54	0x7fe04000 __Ethernet_RAM_segment_end__ = 0x7fe04000
55	0x40000000 __SRAM_segment_start__ = 0x40000000
56	0x40008000 __SRAM_segment_end__ = 0x40008000
57	0x00000000 __FLASH_segment_start__ = 0x0
58	0x00080000 __FLASH_segment_end__ = 0x80000
59	0x00000400 __STACKSIZE__ = 0x400
60	0x00000100 __STACKSIZE_IRQ__ = 0x100
61	0x00000100 __STACKSIZE_FIQ__ = 0x100
62	0x00000000 __STACKSIZE_SVC__ = 0x0
63	0x00000000 __STACKSIZE_ABT__ = 0x0
64	0x00000000 __STACKSIZE_UND__ = 0x0
65	0x00000400 __HEAPSIZE__ = 0x400
66	0x40000000 __vectors_load_start__ = __SRAM_segment_start__
67
68	.vectors 0x40000000 0x3c
69	0x40000000 __vectors_start__ = .
70	(.vectors .vectors.)
71	.vectors 0x40000000 0x3c ARM RAM Debug/Philips_LPC230X_Startup.o
72	0x40000000 _vectors
73	0x4000003c __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors))
74	0x00000001 . = ASSERT (((__vectors_end__ >= __SRAM_segment_start__) && (__vectors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .vectors is too large to fit in SRAM memory segment)
75	0x4000003c __fast_load_start__ = (__vectors_end__ ALIGN 0x4)
76
77	.fast 0x4000003c 0x0
78	0x4000003c __fast_start__ = .
79	(.fast .fast.)
80	0x4000003c __fast_end__ = (__fast_start__ + SIZEOF (.fast))
81	0x00000001 . = ASSERT (((__fast_end__ >= __SRAM_segment_start__) && (__fast_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .fast is too large to fit in SRAM memory segment)
82	0x4000003c __init_load_start__ = (__fast_end__ ALIGN 0x4)
83
84	.init 0x4000003c 0x2e0
85	0x4000003c __init_start__ = .
86	(.init .init.)
87	fill 0x4000003c 0x4 00
88	.init 0x40000040 0x1d0 ARM RAM Debug/crt0.o
89	0x40000040 __start
90	0x40000040 _start
91	.init 0x40000210 0x10c ARM RAM Debug/Philips_LPC230X_Startup.o
92	0x40000210 reset_handler
93	0x40000300 undef_handler
94	0x40000308 pabort_handler
95	0x4000030c dabort_handler
96	0x40000304 swi_handler
97	0x40000310 fiq_handler
98	0x4000031c __init_end__ = (__init_start__ + SIZEOF (.init))
99	0x00000001 . = ASSERT (((__init_end__ >= __SRAM_segment_start__) && (__init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .init is too large to fit in SRAM memory segment)
100	0x4000031c __text_load_start__ = (__init_end__ ALIGN 0x4)
101
102	.text 0x4000031c 0x1154
103	0x4000031c __text_start__ = .
104	(.text .text. .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
105	.text 0x4000031c 0x44 ARM RAM Debug/main_ctl.o
106	0x40000348 ctl_handle_error
107	0x4000031c new_task_code
108	.glue_7 0x40000360 0x0 ARM RAM Debug/main_ctl.o
109	.glue_7t 0x40000360 0x0 ARM RAM Debug/main_ctl.o
110	.text 0x40000360 0x330 ARM RAM Debug/main.o
111	0x40000360 ConfigBlinky
112	0x40000454 task1
113	0x40000500 task2
114	0x400005ac main
115	0x40000418 delay
116	.glue_7 0x40000690 0x0 ARM RAM Debug/main.o
117	.glue_7t 0x40000690 0x0 ARM RAM Debug/main.o
118	.text 0x40000690 0x0 ARM RAM Debug/crt0.o
119	.glue_7 0x40000690 0x0 ARM RAM Debug/crt0.o
120	.glue_7t 0x40000690 0x0 ARM RAM Debug/crt0.o
121	.text 0x40000690 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o
122	.glue_7 0x40000690 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o
123	.glue_7t 0x40000690 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o
124	.text 0x40000690 0x2fc ARM RAM Debug/LPC230x.o
125	0x4000096c ctl_get_ticks_per_second
126	0x40000874 ctl_start_timer
127	0x40000718 get_uart_clk
128	.glue_7 0x4000098c 0x0 ARM RAM Debug/LPC230x.o
129	.glue_7t 0x4000098c 0x0 ARM RAM Debug/LPC230x.o
130	.text 0x4000098c 0x168 ARM RAM Debug/VIC_PL192.o
131	0x40000a74 ctl_unmask_isr
132	0x4000098c ctl_set_isr
133	0x40000ab4 ctl_mask_isr
134	.glue_7 0x40000af4 0x0 ARM RAM Debug/VIC_PL192.o
135	.glue_7t 0x40000af4 0x0 ARM RAM Debug/VIC_PL192.o
136	.text 0x40000af4 0x68 ARM RAM Debug/VIC_PL192_irq_handler.o
137	0x40000af4 irq_handler
138	.glue_7 0x40000b5c 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o
139	.glue_7t 0x40000b5c 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o
140	.text 0x40000b5c 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
141	.text.libctl 0x40000b5c 0x604 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
142	0x40000fe8 ctl_task_remove
143	0x40000eac ctl_private_reschedule
144	0x400010a8 ctl_task_reschedule
145	0x40000fa8 ctl_task_set_priority
146	0x40000bd0 ctl_task_init
147	0x40000c8c ctl_exit_isr
148	0x40000f44 ctl_timeout_wait
149	0x40000e60 ctl_task_die
150	0x40000c64 ctl_get_current_time
151	0x400010d8 ctl_task_run
152	0x40000bf4 ctl_increment_tick_from_isr
153	.glue_7 0x40001160 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
154	.glue_7t 0x40001160 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
155	.text 0x40001160 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o)
156	.text.libctl 0x40001160 0x170 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o)
157	0x400011c8 ctl_private_switch_context
158	0x400012b4 ctl_private_isr_return
159	0x40001238 ctl_private_switch_isr_context
160	0x40001160 ctl_private_init_registers
161	.glue_7 0x400012d0 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o)
162	.glue_7t 0x400012d0 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o)
163	.text 0x400012d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)
164	.text.liblpc2000
165	0x400012d0 0x98 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)
166	0x400012d0 liblpc2000_lpc23xx_get_cclk
167	.glue_7 0x40001368 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)
168	.glue_7t 0x40001368 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)
169	.text 0x40001368 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
170	fill 0x40001368 0x8 00
171	.text.libc 0x40001370 0x30 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
172	0x40001370 ctl_global_interrupts_set
173	0x40001370 libarm_set_irq
174	.glue_7 0x400013a0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
175	.glue_7t 0x400013a0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
176	.text 0x400013a0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
177	.text.libc 0x400013a0 0x30 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
178	0x400013a0 __int32_udiv
179	0x400013a0 __int32_udivmod
180	0x400013a0 __udivsi3
181	.glue_7 0x400013d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
182	.glue_7t 0x400013d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
183	.text 0x400013d0 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
184	.text.libc 0x400013d0 0xa0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
185	0x400013d0 memset
186	.glue_7 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
187	.glue_7t 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
188	0x40001470 __text_end__ = (__text_start__ + SIZEOF (.text))
189	0x00000001 . = ASSERT (((__text_end__ >= __SRAM_segment_start__) && (__text_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .text is too large to fit in SRAM memory segment)
190	0x40001470 __dtors_load_start__ = (__text_end__ ALIGN 0x4)
191
192	.dtors 0x40001470 0x0
193	0x40001470 __dtors_start__ = .
194	(SORT(.dtors.))
195	*(.dtors)
196	0x40001470 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
197	0x00000001 . = ASSERT (((__dtors_end__ >= __SRAM_segment_start__) && (__dtors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .dtors is too large to fit in SRAM memory segment)
198	0x40001470 __ctors_load_start__ = (__dtors_end__ ALIGN 0x4)
199
200	.ctors 0x40001470 0x0
201	0x40001470 __ctors_start__ = .
202	(SORT(.ctors.))
203	*(.ctors)
204	0x40001470 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
205	0x00000001 . = ASSERT (((__ctors_end__ >= __SRAM_segment_start__) && (__ctors_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .ctors is too large to fit in SRAM memory segment)
206	0x40001470 __data_load_start__ = (__ctors_end__ ALIGN 0x4)
207
208	.data 0x40001470 0x0
209	0x40001470 __data_start__ = .
210	(.data .data. .gnu.linkonce.d.*)
211	.data 0x40001470 0x0 ARM RAM Debug/main_ctl.o
212	.data 0x40001470 0x0 ARM RAM Debug/main.o
213	.data 0x40001470 0x0 ARM RAM Debug/crt0.o
214	.data 0x40001470 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o
215	.data 0x40001470 0x0 ARM RAM Debug/LPC230x.o
216	.data 0x40001470 0x0 ARM RAM Debug/VIC_PL192.o
217	.data 0x40001470 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o
218	.data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
219	.data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o)
220	.data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)
221	.data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
222	.data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
223	.data 0x40001470 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
224	0x40001470 __data_end__ = (__data_start__ + SIZEOF (.data))
225	0x00000001 . = ASSERT (((__data_end__ >= __SRAM_segment_start__) && (__data_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .data is too large to fit in SRAM memory segment)
226	0x40001470 __rodata_load_start__ = (__data_end__ ALIGN 0x4)
227
228	.rodata 0x40001470 0x18
229	0x40001470 __rodata_start__ = .
230	(.rodata .rodata. .gnu.linkonce.r.*)
231	.rodata 0x40001470 0x18 ARM RAM Debug/main.o
232	0x40001488 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
233	0x00000001 . = ASSERT (((__rodata_end__ >= __SRAM_segment_start__) && (__rodata_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .rodata is too large to fit in SRAM memory segment)
234	0x40001488 __bss_load_start__ = (__rodata_end__ ALIGN 0x4)
235
236	.bss 0x40001488 0x3c8
237	0x40001488 __bss_start__ = .
238	(.bss .bss. .gnu.linkonce.b.*)
239	.bss 0x40001488 0x0 ARM RAM Debug/main_ctl.o
240	.bss 0x40001488 0x268 ARM RAM Debug/main.o
241	0x4000148c led_2_state
242	0x40001488 led_1_state
243	.bss 0x400016f0 0x0 ARM RAM Debug/crt0.o
244	.bss 0x400016f0 0x0 ARM RAM Debug/Philips_LPC230X_Startup.o
245	.bss 0x400016f0 0x4 ARM RAM Debug/LPC230x.o
246	.bss 0x400016f4 0x0 ARM RAM Debug/VIC_PL192.o
247	.bss 0x400016f4 0x0 ARM RAM Debug/VIC_PL192_irq_handler.o
248	.bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
249	.bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl_arm.o)
250	.bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)
251	.bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
252	.bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
253	.bss 0x400016f4 0x0 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
254	*(COMMON)
255	COMMON 0x400016f4 0x148 ARM RAM Debug/main_ctl.o
256	0x400016f4 new_task_stack
257	0x400017fc new_task
258	0x4000181c main_task
259	COMMON 0x4000183c 0x14 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
260	0x4000183c ctl_interrupt_count
261	0x40001840 ctl_current_time
262	0x40001844 ctl_timeslice_period
263	0x40001848 ctl_task_executing
264	0x4000184c ctl_task_list
265	0x40001850 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
266	0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .bss is too large to fit in SRAM memory segment)
267	0x40001850 __non_init_load_start__ = (__bss_end__ ALIGN 0x4)
268
269	.non_init 0x40001850 0x0
270	0x40001850 __non_init_start__ = .
271	(.non_init .non_init.)
272	0x40001850 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
273	0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .non_init is too large to fit in SRAM memory segment)
274	0x40001850 __heap_load_start__ = (__non_init_end__ ALIGN 0x4)
275
276	.heap 0x40001850 0x400
277	0x40001850 __heap_start__ = .
278	*(.heap)
279	0x40001c50 . = (((__heap_start__ + __HEAPSIZE__) MAX_K .) ALIGN 0x4)
280	fill 0x40001850 0x400 00
281	0x40001c50 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
282	0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .heap is too large to fit in SRAM memory segment)
283	0x40001c50 __stack_load_start__ = (__heap_end__ ALIGN 0x4)
284
285	.stack 0x40001c50 0x400
286	0x40001c50 __stack_start__ = .
287	*(.stack)
288	0x40002050 . = (((__stack_start__ + __STACKSIZE__) MAX_K .) ALIGN 0x4)
289	fill 0x40001c50 0x400 00
290	0x40002050 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
291	0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack is too large to fit in SRAM memory segment)
292	0x40002050 __stack_irq_load_start__ = (__stack_end__ ALIGN 0x4)
293
294	.stack_irq 0x40002050 0x100
295	0x40002050 __stack_irq_start__ = .
296	*(.stack_irq)
297	0x40002150 . = (((__stack_irq_start__ + __STACKSIZE_IRQ__) MAX_K .) ALIGN 0x4)
298	fill 0x40002050 0x100 00
299	0x40002150 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq))
300	0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_irq is too large to fit in SRAM memory segment)
301	0x40002150 __stack_fiq_load_start__ = (__stack_irq_end__ ALIGN 0x4)
302
303	.stack_fiq 0x40002150 0x100
304	0x40002150 __stack_fiq_start__ = .
305	*(.stack_fiq)
306	0x40002250 . = (((__stack_fiq_start__ + __STACKSIZE_FIQ__) MAX_K .) ALIGN 0x4)
307	fill 0x40002150 0x100 00
308	0x40002250 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq))
309	0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_fiq is too large to fit in SRAM memory segment)
310	0x40002250 __stack_svc_load_start__ = (__stack_fiq_end__ ALIGN 0x4)
311
312	.stack_svc 0x40002250 0x0
313	0x40002250 __stack_svc_start__ = .
314	*(.stack_svc)
315	0x40002254 . = (((__stack_svc_start__ + __STACKSIZE_SVC__) MAX_K .) ALIGN 0x4)
316	0x40002250 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc))
317	0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_svc is too large to fit in SRAM memory segment)
318	0x40002250 __stack_abt_load_start__ = (__stack_svc_end__ ALIGN 0x4)
319
320	.stack_abt 0x40002250 0x0
321	0x40002250 __stack_abt_start__ = .
322	*(.stack_abt)
323	0x40002254 . = (((__stack_abt_start__ + __STACKSIZE_ABT__) MAX_K .) ALIGN 0x4)
324	0x40002250 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt))
325	0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_abt is too large to fit in SRAM memory segment)
326	0x40002250 __stack_und_load_start__ = (__stack_abt_end__ ALIGN 0x4)
327
328	.stack_und 0x40002250 0x0
329	0x40002250 __stack_und_start__ = .
330	*(.stack_und)
331	0x40002254 . = (((__stack_und_start__ + __STACKSIZE_UND__) MAX_K .) ALIGN 0x4)
332	0x40002250 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und))
333	0x40002250 __SRAM_segment_used_end__ = ((__stack_abt_end__ ALIGN 0x4) + SIZEOF (.stack_und))
334	0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x8000))), error: .stack_und is too large to fit in SRAM memory segment)
335	START GROUP
336	LOAD ARM RAM Debug/main_ctl.o
337	LOAD ARM RAM Debug/main.o
338	LOAD ARM RAM Debug/crt0.o
339	LOAD ARM RAM Debug/Philips_LPC230X_Startup.o
340	LOAD ARM RAM Debug/LPC230x.o
341	LOAD ARM RAM Debug/VIC_PL192.o
342	LOAD ARM RAM Debug/VIC_PL192_irq_handler.o
343	LOAD /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a
344	LOAD /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a
345	LOAD /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a
346	LOAD /home/phil/CrossWorks_ARM_1_7/lib/libm_v4t_a_le_mt.a
347	LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a
348	LOAD /home/phil/CrossWorks_ARM_1_7/lib/libcpp_v4t_a_le_mt.a
349	LOAD /home/phil/CrossWorks_ARM_1_7/lib/libdebugio_v4t_a_le_mt.a
350	LOAD /home/phil/CrossWorks_ARM_1_7/lib/libc_targetio_impl_v4t_a_le_mt.a
351	LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfprintf_long_v4t_a_le_mt.a
352	LOAD /home/phil/CrossWorks_ARM_1_7/lib/lib_vfscanf_long_v4t_a_le_mt.a
353	END GROUP
354	OUTPUT(ARM RAM Debug/CrossWorks_TaskingLib_Test.elf elf32-littlearm)
355
356	.debug_abbrev 0x00000000 0x404
357	.debug_abbrev 0x00000000 0xf8 ARM RAM Debug/main_ctl.o
358	.debug_abbrev 0x000000f8 0x108 ARM RAM Debug/main.o
359	.debug_abbrev 0x00000200 0x14 ARM RAM Debug/crt0.o
360	.debug_abbrev 0x00000214 0x10 ARM RAM Debug/Philips_LPC230X_Startup.o
361	.debug_abbrev 0x00000224 0xc9 ARM RAM Debug/LPC230x.o
362	.debug_abbrev 0x000002ed 0xab ARM RAM Debug/VIC_PL192.o
363	.debug_abbrev 0x00000398 0x14 ARM RAM Debug/VIC_PL192_irq_handler.o
364	.debug_abbrev 0x000003ac 0x58 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
365
366	.debug_info 0x00000000 0x103e
367	.debug_info 0x00000000 0x362 ARM RAM Debug/main_ctl.o
368	.debug_info 0x00000362 0x3a6 ARM RAM Debug/main.o
369	.debug_info 0x00000708 0xe7 ARM RAM Debug/crt0.o
370	.debug_info 0x000007ef 0x103 ARM RAM Debug/Philips_LPC230X_Startup.o
371	.debug_info 0x000008f2 0x25f ARM RAM Debug/LPC230x.o
372	.debug_info 0x00000b51 0x2ce ARM RAM Debug/VIC_PL192.o
373	.debug_info 0x00000e1f 0x103 ARM RAM Debug/VIC_PL192_irq_handler.o
374	.debug_info 0x00000f22 0x11c /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
375
376	.debug_line 0x00000000 0x742
377	.debug_line 0x00000000 0xbd ARM RAM Debug/main_ctl.o
378	.debug_line 0x000000bd 0xe7 ARM RAM Debug/main.o
379	.debug_line 0x000001a4 0x109 ARM RAM Debug/crt0.o
380	.debug_line 0x000002ad 0x129 ARM RAM Debug/Philips_LPC230X_Startup.o
381	.debug_line 0x000003d6 0x120 ARM RAM Debug/LPC230x.o
382	.debug_line 0x000004f6 0x10a ARM RAM Debug/VIC_PL192.o
383	.debug_line 0x00000600 0xdb ARM RAM Debug/VIC_PL192_irq_handler.o
384	.debug_line 0x000006db 0x67 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
385
386	.debug_frame 0x00000000 0x4b0
387	.debug_frame 0x00000000 0x68 ARM RAM Debug/main_ctl.o
388	.debug_frame 0x00000068 0xec ARM RAM Debug/main.o
389	.debug_frame 0x00000154 0xec ARM RAM Debug/LPC230x.o
390	.debug_frame 0x00000240 0x94 ARM RAM Debug/VIC_PL192.o
391	.debug_frame 0x000002d4 0x17c /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
392	.debug_frame 0x00000450 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libarmdi_v4t_a_le_mt.a(libarm_set_irq.o)
393	.debug_frame 0x00000470 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(__int32_udivmod.o)
394	.debug_frame 0x00000490 0x20 /home/phil/CrossWorks_ARM_1_7/lib/libc_v4t_a_le_mt.a(memset.o)
395
396	.debug_loc 0x00000000 0x3cb
397	.debug_loc 0x00000000 0x54 ARM RAM Debug/main_ctl.o
398	.debug_loc 0x00000054 0xd2 ARM RAM Debug/main.o
399	.debug_loc 0x00000126 0xd2 ARM RAM Debug/LPC230x.o
400	.debug_loc 0x000001f8 0x7e ARM RAM Debug/VIC_PL192.o
401	.debug_loc 0x00000276 0x155 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
402
403	.debug_pubnames
404	0x00000000 0x271
405	.debug_pubnames
406	0x00000000 0x67 ARM RAM Debug/main_ctl.o
407	.debug_pubnames
408	0x00000067 0x6a ARM RAM Debug/main.o
409	.debug_pubnames
410	0x000000d1 0x54 ARM RAM Debug/LPC230x.o
411	.debug_pubnames
412	0x00000125 0x46 ARM RAM Debug/VIC_PL192.o
413	.debug_pubnames
414	0x0000016b 0x106 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
415
416	.debug_aranges 0x00000000 0x108
417	.debug_aranges
418	0x00000000 0x20 ARM RAM Debug/main_ctl.o
419	.debug_aranges
420	0x00000020 0x20 ARM RAM Debug/main.o
421	.debug_aranges
422	0x00000040 0x20 ARM RAM Debug/crt0.o
423	.debug_aranges
424	0x00000060 0x28 ARM RAM Debug/Philips_LPC230X_Startup.o
425	.debug_aranges
426	0x00000088 0x20 ARM RAM Debug/LPC230x.o
427	.debug_aranges
428	0x000000a8 0x20 ARM RAM Debug/VIC_PL192.o
429	.debug_aranges
430	0x000000c8 0x20 ARM RAM Debug/VIC_PL192_irq_handler.o
431	.debug_aranges
432	0x000000e8 0x20 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
433
434	.debug_str 0x00000000 0x17f
435	.debug_str 0x00000000 0x12 ARM RAM Debug/main_ctl.o
436	.debug_str 0x00000012 0x12 ARM RAM Debug/main.o
437	.debug_str 0x00000024 0x7 ARM RAM Debug/VIC_PL192.o
438	.debug_str 0x0000002b 0x154 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
439
440	.comment 0x00000000 0x6c
441	.comment 0x00000000 0x12 ARM RAM Debug/main_ctl.o
442	.comment 0x00000012 0x12 ARM RAM Debug/main.o
443	.comment 0x00000024 0x12 ARM RAM Debug/LPC230x.o
444	.comment 0x00000036 0x12 ARM RAM Debug/VIC_PL192.o
445	.comment 0x00000048 0x12 /home/phil/CrossWorks_ARM_1_7/ctl/lib/libctl_v4t_a_le_mt.a(ctl.o)
446	.comment 0x0000005a 0x12 /home/phil/CrossWorks_ARM_1_7/lib/liblpc2000_v4t_a_le_mt.a(liblpc2000_lpc23xx_get_cclk.o)

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