LPC2300.s

Revision 9, 20.2 kB (checked in by phil, 15 years ago)
EasyWEB example for uVision (original from CD)

Line
1	;/*****************************************************************************/
2	;/* LPC2300.S: Startup file for Philips LPC2300/LPC2400 device series */
3	;/*****************************************************************************/
4	;/* <<< Use Configuration Wizard in Context Menu >>> */
5	;/*****************************************************************************/
6	;/* This file is part of the uVision/ARM development tools. */
7	;/* Copyright (c) 2007 Keil - An ARM Company. All rights reserved. */
8	;/* This software may only be used under the terms of a valid, current, */
9	;/* end user licence from KEIL for a compatible version of KEIL software */
10	;/* development tools. Nothing else gives you the right to use this software. */
11	;/*****************************************************************************/
12
13
14	;/*
15	; * The LPC2300.S code is executed after CPU Reset. This file may be
16	; * translated with the following SET symbols. In uVision these SET
17	; * symbols are entered under Options - ASM - Define.
18	; *
19	; * REMAP: when set the startup code initializes the register MEMMAP
20	; * which overwrites the settings of the CPU configuration pins. The
21	; * startup and interrupt vectors are remapped from:
22	; * 0x00000000 default setting (not remapped)
23	; * 0x40000000 when RAM_MODE is used
24	; *
25	; * RAM_MODE: when set the device is configured for code execution
26	; * from on-chip RAM starting at address 0x40000000.
27	; */
28
29
30	; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
31
32	Mode_USR EQU 0x10
33	Mode_FIQ EQU 0x11
34	Mode_IRQ EQU 0x12
35	Mode_SVC EQU 0x13
36	Mode_ABT EQU 0x17
37	Mode_UND EQU 0x1B
38	Mode_SYS EQU 0x1F
39
40	I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
41	F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
42
43
44	;// <h> Stack Configuration (Stack Sizes in Bytes)
45	;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
46	;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
47	;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
48	;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
49	;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
50	;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
51	;// </h>
52
53	UND_Stack_Size EQU 0x00000000
54	SVC_Stack_Size EQU 0x00000008
55	ABT_Stack_Size EQU 0x00000000
56	FIQ_Stack_Size EQU 0x00000000
57	IRQ_Stack_Size EQU 0x00000100
58	USR_Stack_Size EQU 0x00000400
59
60	ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
61	FIQ_Stack_Size + IRQ_Stack_Size)
62
63	AREA STACK, NOINIT, READWRITE, ALIGN=3
64
65	Stack_Mem SPACE USR_Stack_Size
66	__initial_sp SPACE ISR_Stack_Size
67
68	Stack_Top
69
70
71	;// <h> Heap Configuration
72	;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
73	;// </h>
74
75	Heap_Size EQU 0x00000000
76
77	AREA HEAP, NOINIT, READWRITE, ALIGN=3
78	__heap_base
79	Heap_Mem SPACE Heap_Size
80	__heap_limit
81
82
83	; System Control Block (SCB) Module Definitions
84	SCB_BASE EQU 0xE01FC000 ; SCB Base Address
85	PLLCON_OFS EQU 0x80 ; PLL Control Offset
86	PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset
87	PLLSTAT_OFS EQU 0x88 ; PLL Status Offset
88	PLLFEED_OFS EQU 0x8C ; PLL Feed Offset
89	CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset
90	USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset
91	CLKSRCSEL_OFS EQU 0x10C ; Clock Source Select Reg Offset
92	SCS_OFS EQU 0x1A0 ; System Control and Status Reg Offset
93	PCLKSEL0_OFS EQU 0x1A8 ; Peripheral Clock Select Reg 0 Offset
94	PCLKSEL1_OFS EQU 0x1AC ; Peripheral Clock Select Reg 1 Offset
95
96	; Constants
97	OSCRANGE EQU (1<<4) ; Oscillator Range Select
98	OSCEN EQU (1<<5) ; Main oscillator Enable
99	OSCSTAT EQU (1<<6) ; Main Oscillator Status
100	PLLCON_PLLE EQU (1<<0) ; PLL Enable
101	PLLCON_PLLC EQU (1<<1) ; PLL Connect
102	PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value
103	PLLSTAT_N EQU (0xFF<<16) ; PLL N Value
104	PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status
105
106	;// <e> Clock Setup
107	;// <h> System Controls and Status Register (SCS)
108	;// <o1.4> OSCRANGE: Main Oscillator Range Select
109	;// <0=> 1 MHz to 20 MHz
110	;// <1=> 15 MHz to 24 MHz
111	;// <e1.5> OSCEN: Main Oscillator Enable
112	;// </e>
113	;// </h>
114	;//
115	;// <h> Clock Source Select Register (CLKSRCSEL)
116	;// <o2.0..1> CLKSRC: PLL Clock Source Selection
117	;// <0=> Internal RC oscillator
118	;// <1=> Main oscillator
119	;// <1=> RTC oscillator
120	;// </h>
121	;//
122	;// <h> PLL Configuration Register (PLLCFG)
123	;// <i> PLL_clk = (2* M * PLL_clk_src) / N
124	;// <o3.0..14> MSEL: PLL Multiplier Selection
125	;// <1-32768><#-1>
126	;// <i> M Value
127	;// <o3.16..23> NSEL: PLL Divider Selection
128	;// <1-256><#-1>
129	;// <i> N Value
130	;// </h>
131	;//
132	;// <h> CPU Clock Configuration Register (CCLKCFG)
133	;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL
134	;// <1-256><#-1>
135	;// </h>
136	;//
137	;// <h> USB Clock Configuration Register (USBCLKCFG)
138	;// <o5.0..3> USBSEL: Divide Value for USB Clock from PLL
139	;// <1-16><#-1>
140	;// </h>
141	;//
142	;// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
143	;// <o6.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
144	;// <0=> Pclk = Cclk / 4
145	;// <1=> Pclk = Cclk
146	;// <2=> Pclk = Cclk / 2
147	;// <3=> Pclk = Hclk / 8
148	;// <o6.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
149	;// <0=> Pclk = Cclk / 4
150	;// <1=> Pclk = Cclk
151	;// <2=> Pclk = Cclk / 2
152	;// <3=> Pclk = Hclk / 8
153	;// <o6.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
154	;// <0=> Pclk = Cclk / 4
155	;// <1=> Pclk = Cclk
156	;// <2=> Pclk = Cclk / 2
157	;// <3=> Pclk = Hclk / 8
158	;// <o6.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
159	;// <0=> Pclk = Cclk / 4
160	;// <1=> Pclk = Cclk
161	;// <2=> Pclk = Cclk / 2
162	;// <3=> Pclk = Hclk / 8
163	;// <o6.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
164	;// <0=> Pclk = Cclk / 4
165	;// <1=> Pclk = Cclk
166	;// <2=> Pclk = Cclk / 2
167	;// <3=> Pclk = Hclk / 8
168	;// <o6.10..11> PCLK_PWM0: Peripheral Clock Selection for PWM0
169	;// <0=> Pclk = Cclk / 4
170	;// <1=> Pclk = Cclk
171	;// <2=> Pclk = Cclk / 2
172	;// <3=> Pclk = Hclk / 8
173	;// <o6.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
174	;// <0=> Pclk = Cclk / 4
175	;// <1=> Pclk = Cclk
176	;// <2=> Pclk = Cclk / 2
177	;// <3=> Pclk = Hclk / 8
178	;// <o6.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
179	;// <0=> Pclk = Cclk / 4
180	;// <1=> Pclk = Cclk
181	;// <2=> Pclk = Cclk / 2
182	;// <3=> Pclk = Hclk / 8
183	;// <o6.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
184	;// <0=> Pclk = Cclk / 4
185	;// <1=> Pclk = Cclk
186	;// <2=> Pclk = Cclk / 2
187	;// <3=> Pclk = Hclk / 8
188	;// <o6.18..19> PCLK_RTC: Peripheral Clock Selection for RTC
189	;// <0=> Pclk = Cclk / 4
190	;// <1=> Pclk = Cclk
191	;// <2=> Pclk = Cclk / 2
192	;// <3=> Pclk = Hclk / 8
193	;// <o6.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
194	;// <0=> Pclk = Cclk / 4
195	;// <1=> Pclk = Cclk
196	;// <2=> Pclk = Cclk / 2
197	;// <3=> Pclk = Hclk / 8
198	;// <o6.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
199	;// <0=> Pclk = Cclk / 4
200	;// <1=> Pclk = Cclk
201	;// <2=> Pclk = Cclk / 2
202	;// <3=> Pclk = Hclk / 8
203	;// <o6.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
204	;// <0=> Pclk = Cclk / 4
205	;// <1=> Pclk = Cclk
206	;// <2=> Pclk = Cclk / 2
207	;// <3=> Pclk = Hclk / 8
208	;// <o6.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
209	;// <0=> Pclk = Cclk / 4
210	;// <1=> Pclk = Cclk
211	;// <2=> Pclk = Cclk / 2
212	;// <3=> Pclk = Hclk / 6
213	;// <o6.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
214	;// <0=> Pclk = Cclk / 4
215	;// <1=> Pclk = Cclk
216	;// <2=> Pclk = Cclk / 2
217	;// <3=> Pclk = Hclk / 6
218	;// <o6.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
219	;// <0=> Pclk = Cclk / 4
220	;// <1=> Pclk = Cclk
221	;// <2=> Pclk = Cclk / 2
222	;// <3=> Pclk = Hclk / 6
223	;// </h>
224	;//
225	;// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
226	;// <o7.0..1> PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM
227	;// <0=> Pclk = Cclk / 4
228	;// <1=> Pclk = Cclk
229	;// <2=> Pclk = Cclk / 2
230	;// <3=> Pclk = Hclk / 8
231	;// <o7.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
232	;// <0=> Pclk = Cclk / 4
233	;// <1=> Pclk = Cclk
234	;// <2=> Pclk = Cclk / 2
235	;// <3=> Pclk = Hclk / 8
236	;// <o7.4..5> PCLK_PCB: Peripheral Clock Selection for Pin Connect Block
237	;// <0=> Pclk = Cclk / 4
238	;// <1=> Pclk = Cclk
239	;// <2=> Pclk = Cclk / 2
240	;// <3=> Pclk = Hclk / 8
241	;// <o7.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
242	;// <0=> Pclk = Cclk / 4
243	;// <1=> Pclk = Cclk
244	;// <2=> Pclk = Cclk / 2
245	;// <3=> Pclk = Hclk / 8
246	;// <o7.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
247	;// <0=> Pclk = Cclk / 4
248	;// <1=> Pclk = Cclk
249	;// <2=> Pclk = Cclk / 2
250	;// <3=> Pclk = Hclk / 8
251	;// <o7.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
252	;// <0=> Pclk = Cclk / 4
253	;// <1=> Pclk = Cclk
254	;// <2=> Pclk = Cclk / 2
255	;// <3=> Pclk = Hclk / 8
256	;// <o7.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
257	;// <0=> Pclk = Cclk / 4
258	;// <1=> Pclk = Cclk
259	;// <2=> Pclk = Cclk / 2
260	;// <3=> Pclk = Hclk / 8
261	;// <o7.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
262	;// <0=> Pclk = Cclk / 4
263	;// <1=> Pclk = Cclk
264	;// <2=> Pclk = Cclk / 2
265	;// <3=> Pclk = Hclk / 8
266	;// <o7.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
267	;// <0=> Pclk = Cclk / 4
268	;// <1=> Pclk = Cclk
269	;// <2=> Pclk = Cclk / 2
270	;// <3=> Pclk = Hclk / 8
271	;// <o7.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
272	;// <0=> Pclk = Cclk / 4
273	;// <1=> Pclk = Cclk
274	;// <2=> Pclk = Cclk / 2
275	;// <3=> Pclk = Hclk / 8
276	;// <o7.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
277	;// <0=> Pclk = Cclk / 4
278	;// <1=> Pclk = Cclk
279	;// <2=> Pclk = Cclk / 2
280	;// <3=> Pclk = Hclk / 8
281	;// <o7.24..25> PCLK_MCI: Peripheral Clock Selection for MCI
282	;// <0=> Pclk = Cclk / 4
283	;// <1=> Pclk = Cclk
284	;// <2=> Pclk = Cclk / 2
285	;// <3=> Pclk = Hclk / 8
286	;// <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block
287	;// <0=> Pclk = Cclk / 4
288	;// <1=> Pclk = Cclk
289	;// <2=> Pclk = Cclk / 2
290	;// <3=> Pclk = Hclk / 8
291	;// </h>
292	;// </e>
293	CLOCK_SETUP EQU 1
294	SCS_Val EQU 0x00000020
295	CLKSRCSEL_Val EQU 0x00000001
296	PLLCFG_Val EQU 0x0000000B
297	CCLKCFG_Val EQU 0x00000005
298	USBCLKCFG_Val EQU 0x00000005
299	PCLKSEL0_Val EQU 0x00000000
300	PCLKSEL1_Val EQU 0x00000000
301
302
303	; Memory Accelerator Module (MAM) definitions
304	MAM_BASE EQU 0xE01FC000 ; MAM Base Address
305	MAMCR_OFS EQU 0x00 ; MAM Control Offset
306	MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
307
308	;// <e> MAM Setup
309	;// <o1.0..1> MAM Control
310	;// <0=> Disabled
311	;// <1=> Partially Enabled
312	;// <2=> Fully Enabled
313	;// <i> Mode
314	;// <o2.0..2> MAM Timing
315	;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
316	;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
317	;// <i> Fetch Cycles
318	;// </e>
319	MAM_SETUP EQU 1
320	MAMCR_Val EQU 0x00000002
321	MAMTIM_Val EQU 0x00000004
322
323
324	; Area Definition and Entry Point
325	; Startup Code must be linked first at Address at which it expects to run.
326
327	AREA RESET, CODE, READONLY
328	ARM
329
330
331	; Exception Vectors
332	; Mapped to Address 0.
333	; Absolute addressing mode must be used.
334	; Dummy Handlers are implemented as infinite loops which can be modified.
335
336	Vectors LDR PC, Reset_Addr
337	LDR PC, Undef_Addr
338	LDR PC, SWI_Addr
339	LDR PC, PAbt_Addr
340	LDR PC, DAbt_Addr
341	NOP ; Reserved Vector
342	; LDR PC, IRQ_Addr
343	LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr
344	LDR PC, FIQ_Addr
345
346	Reset_Addr DCD Reset_Handler
347	Undef_Addr DCD Undef_Handler
348	SWI_Addr DCD SWI_Handler
349	PAbt_Addr DCD PAbt_Handler
350	DAbt_Addr DCD DAbt_Handler
351	DCD 0 ; Reserved Address
352	IRQ_Addr DCD IRQ_Handler
353	FIQ_Addr DCD FIQ_Handler
354
355	Undef_Handler B Undef_Handler
356	SWI_Handler B SWI_Handler
357	PAbt_Handler B PAbt_Handler
358	DAbt_Handler B DAbt_Handler
359	IRQ_Handler B IRQ_Handler
360	FIQ_Handler B FIQ_Handler
361
362
363	; Reset Handler
364
365	EXPORT Reset_Handler
366	Reset_Handler
367
368
369	; Setup Clock
370	IF CLOCK_SETUP != 0
371	LDR R0, =SCB_BASE
372	MOV R1, #0xAA
373	MOV R2, #0x55
374
375	; Configure and Enable PLL
376	LDR R3, =SCS_Val ; Enable main oscillator
377	STR R3, [R0, #SCS_OFS]
378
379	IF (SCS_Val:AND:OSCEN) != 0
380	OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize
381	ANDS R3, R3, #OSCSTAT
382	BEQ OSC_Loop
383	ENDIF
384
385	LDR R3, =CLKSRCSEL_Val ; Select PLL source clock
386	STR R3, [R0, #CLKSRCSEL_OFS]
387	LDR R3, =PLLCFG_Val
388	STR R3, [R0, #PLLCFG_OFS]
389	STR R1, [R0, #PLLFEED_OFS]
390	STR R2, [R0, #PLLFEED_OFS]
391	MOV R3, #PLLCON_PLLE
392	STR R3, [R0, #PLLCON_OFS]
393	STR R1, [R0, #PLLFEED_OFS]
394	STR R2, [R0, #PLLFEED_OFS]
395
396	; Wait until PLL Locked
397	PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
398	ANDS R3, R3, #PLLSTAT_PLOCK
399	BEQ PLL_Loop
400
401	M_N_Lock LDR R3, [R0, #PLLSTAT_OFS]
402	LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N)
403	AND R3, R3, R4
404	LDR R4, =PLLCFG_Val
405	EORS R3, R3, R4
406	BNE M_N_Lock
407
408	; Setup CPU clock divider
409	MOV R3, #CCLKCFG_Val
410	STR R3, [R0, #CCLKCFG_OFS]
411
412	; Setup USB clock divider
413	LDR R3, =USBCLKCFG_Val
414	STR R3, [R0, #USBCLKCFG_OFS]
415
416	; Setup Peripheral Clock
417	LDR R3, =PCLKSEL0_Val
418	STR R3, [R0, #PCLKSEL0_OFS]
419	LDR R3, =PCLKSEL1_Val
420	STR R3, [R0, #PCLKSEL1_OFS]
421
422	; Switch to PLL Clock
423	MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
424	STR R3, [R0, #PLLCON_OFS]
425	STR R1, [R0, #PLLFEED_OFS]
426	STR R2, [R0, #PLLFEED_OFS]
427	ENDIF ; CLOCK_SETUP
428
429
430	; Setup MAM
431	IF MAM_SETUP != 0
432	LDR R0, =MAM_BASE
433	MOV R1, #MAMTIM_Val
434	STR R1, [R0, #MAMTIM_OFS]
435	MOV R1, #MAMCR_Val
436	STR R1, [R0, #MAMCR_OFS]
437	ENDIF ; MAM_SETUP
438
439
440	; Memory Mapping (when Interrupt Vectors are in RAM)
441	MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
442	IF :DEF:REMAP
443	LDR R0, =MEMMAP
444	IF :DEF:RAM_MODE
445	MOV R1, #2
446	ELSE
447	MOV R1, #1
448	ENDIF
449	STR R1, [R0]
450	ENDIF
451
452
453	; Initialise Interrupt System
454	; ...
455
456
457	; Setup Stack for each mode
458
459	LDR R0, =Stack_Top
460
461	; Enter Undefined Instruction Mode and set its Stack Pointer
462	MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
463	MOV SP, R0
464	SUB R0, R0, #UND_Stack_Size
465
466	; Enter Abort Mode and set its Stack Pointer
467	MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
468	MOV SP, R0
469	SUB R0, R0, #ABT_Stack_Size
470
471	; Enter FIQ Mode and set its Stack Pointer
472	MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
473	MOV SP, R0
474	SUB R0, R0, #FIQ_Stack_Size
475
476	; Enter IRQ Mode and set its Stack Pointer
477	MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
478	MOV SP, R0
479	SUB R0, R0, #IRQ_Stack_Size
480
481	; Enter Supervisor Mode and set its Stack Pointer
482	MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
483	MOV SP, R0
484	SUB R0, R0, #SVC_Stack_Size
485
486	; Enter User Mode and set its Stack Pointer
487	MSR CPSR_c, #Mode_USR
488	IF :DEF:__MICROLIB
489
490	EXPORT __initial_sp
491
492	ELSE
493
494	MOV SP, R0
495	SUB SL, SP, #USR_Stack_Size
496
497	ENDIF
498
499
500	; Enter the C code
501
502	IMPORT __main
503	LDR R0, =__main
504	BX R0
505
506
507	IF :DEF:__MICROLIB
508
509	EXPORT __heap_base
510	EXPORT __heap_limit
511
512	ELSE
513	; User Initial Stack & Heap
514	AREA \|.text\|, CODE, READONLY
515
516	IMPORT __use_two_region_memory
517	EXPORT __user_initial_stackheap
518	__user_initial_stackheap
519
520	LDR R0, = Heap_Mem
521	LDR R1, =(Stack_Mem + USR_Stack_Size)
522	LDR R2, = (Heap_Mem + Heap_Size)
523	LDR R3, = Stack_Mem
524	BX LR
525	ENDIF
526
527
528	END

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