LPC23xx.h

Revision 10, 72.5 kB (checked in by phil, 15 years ago)
First compileable version of EasyWeb? for CrossWorks? ARM Compiler, without TCPClockHandler - runs only once after startup.

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1	/******************************************************************************
2	* LPC23xx.h: Header file for NXP LPC23xx/24xx Family Microprocessors
3	* The header file is the super set of all hardware definition of the
4	* peripherals for the LPC23xx/24xx family microprocessor.
5	*
6	* Copyright(C) 2006, NXP Semiconductor
7	* All rights reserved.
8	*
9	* History
10	* 2005.10.01 ver 1.00 Prelimnary version, first Release
11	*
12	******************************************************************************/
13
14	#ifndef __LPC23xx_H
15	#define __LPC23xx_H
16
17	/* Vectored Interrupt Controller (VIC) */
18	#define VIC_BASE_ADDR 0xFFFFF000
19	#define VICIRQStatus ((volatile unsigned long )(VIC_BASE_ADDR + 0x000))
20	#define VICFIQStatus ((volatile unsigned long )(VIC_BASE_ADDR + 0x004))
21	#define VICRawIntr ((volatile unsigned long )(VIC_BASE_ADDR + 0x008))
22	#define VICIntSelect ((volatile unsigned long )(VIC_BASE_ADDR + 0x00C))
23	#define VICIntEnable ((volatile unsigned long )(VIC_BASE_ADDR + 0x010))
24	#define VICIntEnClr ((volatile unsigned long )(VIC_BASE_ADDR + 0x014))
25	#define VICSoftInt ((volatile unsigned long )(VIC_BASE_ADDR + 0x018))
26	#define VICSoftIntClr ((volatile unsigned long )(VIC_BASE_ADDR + 0x01C))
27	#define VICProtection ((volatile unsigned long )(VIC_BASE_ADDR + 0x020))
28	#define VICSWPrioMask ((volatile unsigned long )(VIC_BASE_ADDR + 0x024))
29
30	#define VICVectAddr0 ((volatile unsigned long )(VIC_BASE_ADDR + 0x100))
31	#define VICVectAddr1 ((volatile unsigned long )(VIC_BASE_ADDR + 0x104))
32	#define VICVectAddr2 ((volatile unsigned long )(VIC_BASE_ADDR + 0x108))
33	#define VICVectAddr3 ((volatile unsigned long )(VIC_BASE_ADDR + 0x10C))
34	#define VICVectAddr4 ((volatile unsigned long )(VIC_BASE_ADDR + 0x110))
35	#define VICVectAddr5 ((volatile unsigned long )(VIC_BASE_ADDR + 0x114))
36	#define VICVectAddr6 ((volatile unsigned long )(VIC_BASE_ADDR + 0x118))
37	#define VICVectAddr7 ((volatile unsigned long )(VIC_BASE_ADDR + 0x11C))
38	#define VICVectAddr8 ((volatile unsigned long )(VIC_BASE_ADDR + 0x120))
39	#define VICVectAddr9 ((volatile unsigned long )(VIC_BASE_ADDR + 0x124))
40	#define VICVectAddr10 ((volatile unsigned long )(VIC_BASE_ADDR + 0x128))
41	#define VICVectAddr11 ((volatile unsigned long )(VIC_BASE_ADDR + 0x12C))
42	#define VICVectAddr12 ((volatile unsigned long )(VIC_BASE_ADDR + 0x130))
43	#define VICVectAddr13 ((volatile unsigned long )(VIC_BASE_ADDR + 0x134))
44	#define VICVectAddr14 ((volatile unsigned long )(VIC_BASE_ADDR + 0x138))
45	#define VICVectAddr15 ((volatile unsigned long )(VIC_BASE_ADDR + 0x13C))
46	#define VICVectAddr16 ((volatile unsigned long )(VIC_BASE_ADDR + 0x140))
47	#define VICVectAddr17 ((volatile unsigned long )(VIC_BASE_ADDR + 0x144))
48	#define VICVectAddr18 ((volatile unsigned long )(VIC_BASE_ADDR + 0x148))
49	#define VICVectAddr19 ((volatile unsigned long )(VIC_BASE_ADDR + 0x14C))
50	#define VICVectAddr20 ((volatile unsigned long )(VIC_BASE_ADDR + 0x150))
51	#define VICVectAddr21 ((volatile unsigned long )(VIC_BASE_ADDR + 0x154))
52	#define VICVectAddr22 ((volatile unsigned long )(VIC_BASE_ADDR + 0x158))
53	#define VICVectAddr23 ((volatile unsigned long )(VIC_BASE_ADDR + 0x15C))
54	#define VICVectAddr24 ((volatile unsigned long )(VIC_BASE_ADDR + 0x160))
55	#define VICVectAddr25 ((volatile unsigned long )(VIC_BASE_ADDR + 0x164))
56	#define VICVectAddr26 ((volatile unsigned long )(VIC_BASE_ADDR + 0x168))
57	#define VICVectAddr27 ((volatile unsigned long )(VIC_BASE_ADDR + 0x16C))
58	#define VICVectAddr28 ((volatile unsigned long )(VIC_BASE_ADDR + 0x170))
59	#define VICVectAddr29 ((volatile unsigned long )(VIC_BASE_ADDR + 0x174))
60	#define VICVectAddr30 ((volatile unsigned long )(VIC_BASE_ADDR + 0x178))
61	#define VICVectAddr31 ((volatile unsigned long )(VIC_BASE_ADDR + 0x17C))
62
63	/* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
64	these registers are known as "VICVectPriority(x)". */
65	#define VICVectCntl0 ((volatile unsigned long )(VIC_BASE_ADDR + 0x200))
66	#define VICVectCntl1 ((volatile unsigned long )(VIC_BASE_ADDR + 0x204))
67	#define VICVectCntl2 ((volatile unsigned long )(VIC_BASE_ADDR + 0x208))
68	#define VICVectCntl3 ((volatile unsigned long )(VIC_BASE_ADDR + 0x20C))
69	#define VICVectCntl4 ((volatile unsigned long )(VIC_BASE_ADDR + 0x210))
70	#define VICVectCntl5 ((volatile unsigned long )(VIC_BASE_ADDR + 0x214))
71	#define VICVectCntl6 ((volatile unsigned long )(VIC_BASE_ADDR + 0x218))
72	#define VICVectCntl7 ((volatile unsigned long )(VIC_BASE_ADDR + 0x21C))
73	#define VICVectCntl8 ((volatile unsigned long )(VIC_BASE_ADDR + 0x220))
74	#define VICVectCntl9 ((volatile unsigned long )(VIC_BASE_ADDR + 0x224))
75	#define VICVectCntl10 ((volatile unsigned long )(VIC_BASE_ADDR + 0x228))
76	#define VICVectCntl11 ((volatile unsigned long )(VIC_BASE_ADDR + 0x22C))
77	#define VICVectCntl12 ((volatile unsigned long )(VIC_BASE_ADDR + 0x230))
78	#define VICVectCntl13 ((volatile unsigned long )(VIC_BASE_ADDR + 0x234))
79	#define VICVectCntl14 ((volatile unsigned long )(VIC_BASE_ADDR + 0x238))
80	#define VICVectCntl15 ((volatile unsigned long )(VIC_BASE_ADDR + 0x23C))
81	#define VICVectCntl16 ((volatile unsigned long )(VIC_BASE_ADDR + 0x240))
82	#define VICVectCntl17 ((volatile unsigned long )(VIC_BASE_ADDR + 0x244))
83	#define VICVectCntl18 ((volatile unsigned long )(VIC_BASE_ADDR + 0x248))
84	#define VICVectCntl19 ((volatile unsigned long )(VIC_BASE_ADDR + 0x24C))
85	#define VICVectCntl20 ((volatile unsigned long )(VIC_BASE_ADDR + 0x250))
86	#define VICVectCntl21 ((volatile unsigned long )(VIC_BASE_ADDR + 0x254))
87	#define VICVectCntl22 ((volatile unsigned long )(VIC_BASE_ADDR + 0x258))
88	#define VICVectCntl23 ((volatile unsigned long )(VIC_BASE_ADDR + 0x25C))
89	#define VICVectCntl24 ((volatile unsigned long )(VIC_BASE_ADDR + 0x260))
90	#define VICVectCntl25 ((volatile unsigned long )(VIC_BASE_ADDR + 0x264))
91	#define VICVectCntl26 ((volatile unsigned long )(VIC_BASE_ADDR + 0x268))
92	#define VICVectCntl27 ((volatile unsigned long )(VIC_BASE_ADDR + 0x26C))
93	#define VICVectCntl28 ((volatile unsigned long )(VIC_BASE_ADDR + 0x270))
94	#define VICVectCntl29 ((volatile unsigned long )(VIC_BASE_ADDR + 0x274))
95	#define VICVectCntl30 ((volatile unsigned long )(VIC_BASE_ADDR + 0x278))
96	#define VICVectCntl31 ((volatile unsigned long )(VIC_BASE_ADDR + 0x27C))
97
98	#define VICVectAddr ((volatile unsigned long )(VIC_BASE_ADDR + 0xF00))
99
100
101	/* Pin Connect Block */
102	#define PINSEL_BASE_ADDR 0xE002C000
103	#define PINSEL0 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x00))
104	#define PINSEL1 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x04))
105	#define PINSEL2 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x08))
106	#define PINSEL3 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x0C))
107	#define PINSEL4 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x10))
108	#define PINSEL5 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x14))
109	#define PINSEL6 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x18))
110	#define PINSEL7 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x1C))
111	#define PINSEL8 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x20))
112	#define PINSEL9 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x24))
113	#define PINSEL10 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x28))
114
115	#define PINMODE0 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x40))
116	#define PINMODE1 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x44))
117	#define PINMODE2 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x48))
118	#define PINMODE3 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x4C))
119	#define PINMODE4 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x50))
120	#define PINMODE5 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x54))
121	#define PINMODE6 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x58))
122	#define PINMODE7 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x5C))
123	#define PINMODE8 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x60))
124	#define PINMODE9 ((volatile unsigned long )(PINSEL_BASE_ADDR + 0x64))
125
126	/* General Purpose Input/Output (GPIO) */
127	#define GPIO_BASE_ADDR 0xE0028000
128	#define IOPIN0 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x00))
129	#define IOSET0 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x04))
130	#define IODIR0 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x08))
131	#define IOCLR0 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x0C))
132	#define IOPIN1 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x10))
133	#define IOSET1 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x14))
134	#define IODIR1 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x18))
135	#define IOCLR1 ((volatile unsigned long )(GPIO_BASE_ADDR + 0x1C))
136
137	/* GPIO Interrupt Registers */
138	#define IO0_INT_EN_R ((volatile unsigned long )(GPIO_BASE_ADDR + 0x90))
139	#define IO0_INT_EN_F ((volatile unsigned long )(GPIO_BASE_ADDR + 0x94))
140	#define IO0_INT_STAT_R ((volatile unsigned long )(GPIO_BASE_ADDR + 0x84))
141	#define IO0_INT_STAT_F ((volatile unsigned long )(GPIO_BASE_ADDR + 0x88))
142	#define IO0_INT_CLR ((volatile unsigned long )(GPIO_BASE_ADDR + 0x8C))
143
144	#define IO2_INT_EN_R ((volatile unsigned long )(GPIO_BASE_ADDR + 0xB0))
145	#define IO2_INT_EN_F ((volatile unsigned long )(GPIO_BASE_ADDR + 0xB4))
146	#define IO2_INT_STAT_R ((volatile unsigned long )(GPIO_BASE_ADDR + 0xA4))
147	#define IO2_INT_STAT_F ((volatile unsigned long )(GPIO_BASE_ADDR + 0xA8))
148	#define IO2_INT_CLR ((volatile unsigned long )(GPIO_BASE_ADDR + 0xAC))
149
150	#define IO_INT_STAT ((volatile unsigned long )(GPIO_BASE_ADDR + 0x80))
151
152	#define PARTCFG_BASE_ADDR 0x3FFF8000
153	#define PARTCFG ((volatile unsigned long )(PARTCFG_BASE_ADDR + 0x00))
154
155	/* Fast I/O setup */
156	#define FIO_BASE_ADDR 0x3FFFC000
157	#define FIO0DIR ((volatile unsigned long )(FIO_BASE_ADDR + 0x00))
158	#define FIO0MASK ((volatile unsigned long )(FIO_BASE_ADDR + 0x10))
159	#define FIO0PIN ((volatile unsigned long )(FIO_BASE_ADDR + 0x14))
160	#define FIO0SET ((volatile unsigned long )(FIO_BASE_ADDR + 0x18))
161	#define FIO0CLR ((volatile unsigned long )(FIO_BASE_ADDR + 0x1C))
162
163	#define FIO1DIR ((volatile unsigned long )(FIO_BASE_ADDR + 0x20))
164	#define FIO1MASK ((volatile unsigned long )(FIO_BASE_ADDR + 0x30))
165	#define FIO1PIN ((volatile unsigned long )(FIO_BASE_ADDR + 0x34))
166	#define FIO1SET ((volatile unsigned long )(FIO_BASE_ADDR + 0x38))
167	#define FIO1CLR ((volatile unsigned long )(FIO_BASE_ADDR + 0x3C))
168
169	#define FIO2DIR ((volatile unsigned long )(FIO_BASE_ADDR + 0x40))
170	#define FIO2MASK ((volatile unsigned long )(FIO_BASE_ADDR + 0x50))
171	#define FIO2PIN ((volatile unsigned long )(FIO_BASE_ADDR + 0x54))
172	#define FIO2SET ((volatile unsigned long )(FIO_BASE_ADDR + 0x58))
173	#define FIO2CLR ((volatile unsigned long )(FIO_BASE_ADDR + 0x5C))
174
175	#define FIO3DIR ((volatile unsigned long )(FIO_BASE_ADDR + 0x60))
176	#define FIO3MASK ((volatile unsigned long )(FIO_BASE_ADDR + 0x70))
177	#define FIO3PIN ((volatile unsigned long )(FIO_BASE_ADDR + 0x74))
178	#define FIO3SET ((volatile unsigned long )(FIO_BASE_ADDR + 0x78))
179	#define FIO3CLR ((volatile unsigned long )(FIO_BASE_ADDR + 0x7C))
180
181	#define FIO4DIR ((volatile unsigned long )(FIO_BASE_ADDR + 0x80))
182	#define FIO4MASK ((volatile unsigned long )(FIO_BASE_ADDR + 0x90))
183	#define FIO4PIN ((volatile unsigned long )(FIO_BASE_ADDR + 0x94))
184	#define FIO4SET ((volatile unsigned long )(FIO_BASE_ADDR + 0x98))
185	#define FIO4CLR ((volatile unsigned long )(FIO_BASE_ADDR + 0x9C))
186
187	/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
188	#define FIO0DIR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x00))
189	#define FIO1DIR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x20))
190	#define FIO2DIR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x40))
191	#define FIO3DIR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x60))
192	#define FIO4DIR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x80))
193
194	#define FIO0DIR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x01))
195	#define FIO1DIR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x21))
196	#define FIO2DIR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x41))
197	#define FIO3DIR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x61))
198	#define FIO4DIR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x81))
199
200	#define FIO0DIR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x02))
201	#define FIO1DIR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x22))
202	#define FIO2DIR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x42))
203	#define FIO3DIR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x62))
204	#define FIO4DIR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x82))
205
206	#define FIO0DIR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x03))
207	#define FIO1DIR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x23))
208	#define FIO2DIR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x43))
209	#define FIO3DIR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x63))
210	#define FIO4DIR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x83))
211
212	#define FIO0DIRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x00))
213	#define FIO1DIRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x20))
214	#define FIO2DIRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x40))
215	#define FIO3DIRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x60))
216	#define FIO4DIRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x80))
217
218	#define FIO0DIRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x02))
219	#define FIO1DIRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x22))
220	#define FIO2DIRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x42))
221	#define FIO3DIRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x62))
222	#define FIO4DIRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x82))
223
224	#define FIO0MASK0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x10))
225	#define FIO1MASK0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x30))
226	#define FIO2MASK0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x50))
227	#define FIO3MASK0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x70))
228	#define FIO4MASK0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x90))
229
230	#define FIO0MASK1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x11))
231	#define FIO1MASK1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x21))
232	#define FIO2MASK1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x51))
233	#define FIO3MASK1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x71))
234	#define FIO4MASK1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x91))
235
236	#define FIO0MASK2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x12))
237	#define FIO1MASK2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x32))
238	#define FIO2MASK2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x52))
239	#define FIO3MASK2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x72))
240	#define FIO4MASK2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x92))
241
242	#define FIO0MASK3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x13))
243	#define FIO1MASK3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x33))
244	#define FIO2MASK3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x53))
245	#define FIO3MASK3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x73))
246	#define FIO4MASK3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x93))
247
248	#define FIO0MASKL ((volatile unsigned short )(FIO_BASE_ADDR + 0x10))
249	#define FIO1MASKL ((volatile unsigned short )(FIO_BASE_ADDR + 0x30))
250	#define FIO2MASKL ((volatile unsigned short )(FIO_BASE_ADDR + 0x50))
251	#define FIO3MASKL ((volatile unsigned short )(FIO_BASE_ADDR + 0x70))
252	#define FIO4MASKL ((volatile unsigned short )(FIO_BASE_ADDR + 0x90))
253
254	#define FIO0MASKU ((volatile unsigned short )(FIO_BASE_ADDR + 0x12))
255	#define FIO1MASKU ((volatile unsigned short )(FIO_BASE_ADDR + 0x32))
256	#define FIO2MASKU ((volatile unsigned short )(FIO_BASE_ADDR + 0x52))
257	#define FIO3MASKU ((volatile unsigned short )(FIO_BASE_ADDR + 0x72))
258	#define FIO4MASKU ((volatile unsigned short )(FIO_BASE_ADDR + 0x92))
259
260	#define FIO0PIN0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x14))
261	#define FIO1PIN0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x34))
262	#define FIO2PIN0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x54))
263	#define FIO3PIN0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x74))
264	#define FIO4PIN0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x94))
265
266	#define FIO0PIN1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x15))
267	#define FIO1PIN1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x25))
268	#define FIO2PIN1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x55))
269	#define FIO3PIN1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x75))
270	#define FIO4PIN1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x95))
271
272	#define FIO0PIN2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x16))
273	#define FIO1PIN2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x36))
274	#define FIO2PIN2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x56))
275	#define FIO3PIN2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x76))
276	#define FIO4PIN2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x96))
277
278	#define FIO0PIN3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x17))
279	#define FIO1PIN3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x37))
280	#define FIO2PIN3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x57))
281	#define FIO3PIN3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x77))
282	#define FIO4PIN3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x97))
283
284	#define FIO0PINL ((volatile unsigned short )(FIO_BASE_ADDR + 0x14))
285	#define FIO1PINL ((volatile unsigned short )(FIO_BASE_ADDR + 0x34))
286	#define FIO2PINL ((volatile unsigned short )(FIO_BASE_ADDR + 0x54))
287	#define FIO3PINL ((volatile unsigned short )(FIO_BASE_ADDR + 0x74))
288	#define FIO4PINL ((volatile unsigned short )(FIO_BASE_ADDR + 0x94))
289
290	#define FIO0PINU ((volatile unsigned short )(FIO_BASE_ADDR + 0x16))
291	#define FIO1PINU ((volatile unsigned short )(FIO_BASE_ADDR + 0x36))
292	#define FIO2PINU ((volatile unsigned short )(FIO_BASE_ADDR + 0x56))
293	#define FIO3PINU ((volatile unsigned short )(FIO_BASE_ADDR + 0x76))
294	#define FIO4PINU ((volatile unsigned short )(FIO_BASE_ADDR + 0x96))
295
296	#define FIO0SET0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x18))
297	#define FIO1SET0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x38))
298	#define FIO2SET0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x58))
299	#define FIO3SET0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x78))
300	#define FIO4SET0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x98))
301
302	#define FIO0SET1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x19))
303	#define FIO1SET1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x29))
304	#define FIO2SET1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x59))
305	#define FIO3SET1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x79))
306	#define FIO4SET1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x99))
307
308	#define FIO0SET2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x1A))
309	#define FIO1SET2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x3A))
310	#define FIO2SET2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x5A))
311	#define FIO3SET2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x7A))
312	#define FIO4SET2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x9A))
313
314	#define FIO0SET3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x1B))
315	#define FIO1SET3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x3B))
316	#define FIO2SET3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x5B))
317	#define FIO3SET3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x7B))
318	#define FIO4SET3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x9B))
319
320	#define FIO0SETL ((volatile unsigned short )(FIO_BASE_ADDR + 0x18))
321	#define FIO1SETL ((volatile unsigned short )(FIO_BASE_ADDR + 0x38))
322	#define FIO2SETL ((volatile unsigned short )(FIO_BASE_ADDR + 0x58))
323	#define FIO3SETL ((volatile unsigned short )(FIO_BASE_ADDR + 0x78))
324	#define FIO4SETL ((volatile unsigned short )(FIO_BASE_ADDR + 0x98))
325
326	#define FIO0SETU ((volatile unsigned short )(FIO_BASE_ADDR + 0x1A))
327	#define FIO1SETU ((volatile unsigned short )(FIO_BASE_ADDR + 0x3A))
328	#define FIO2SETU ((volatile unsigned short )(FIO_BASE_ADDR + 0x5A))
329	#define FIO3SETU ((volatile unsigned short )(FIO_BASE_ADDR + 0x7A))
330	#define FIO4SETU ((volatile unsigned short )(FIO_BASE_ADDR + 0x9A))
331
332	#define FIO0CLR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x1C))
333	#define FIO1CLR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x3C))
334	#define FIO2CLR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x5C))
335	#define FIO3CLR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x7C))
336	#define FIO4CLR0 ((volatile unsigned char )(FIO_BASE_ADDR + 0x9C))
337
338	#define FIO0CLR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x1D))
339	#define FIO1CLR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x2D))
340	#define FIO2CLR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x5D))
341	#define FIO3CLR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x7D))
342	#define FIO4CLR1 ((volatile unsigned char )(FIO_BASE_ADDR + 0x9D))
343
344	#define FIO0CLR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x1E))
345	#define FIO1CLR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x3E))
346	#define FIO2CLR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x5E))
347	#define FIO3CLR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x7E))
348	#define FIO4CLR2 ((volatile unsigned char )(FIO_BASE_ADDR + 0x9E))
349
350	#define FIO0CLR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x1F))
351	#define FIO1CLR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x3F))
352	#define FIO2CLR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x5F))
353	#define FIO3CLR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x7F))
354	#define FIO4CLR3 ((volatile unsigned char )(FIO_BASE_ADDR + 0x9F))
355
356	#define FIO0CLRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x1C))
357	#define FIO1CLRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x3C))
358	#define FIO2CLRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x5C))
359	#define FIO3CLRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x7C))
360	#define FIO4CLRL ((volatile unsigned short )(FIO_BASE_ADDR + 0x9C))
361
362	#define FIO0CLRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x1E))
363	#define FIO1CLRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x3E))
364	#define FIO2CLRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x5E))
365	#define FIO3CLRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x7E))
366	#define FIO4CLRU ((volatile unsigned short )(FIO_BASE_ADDR + 0x9E))
367
368
369	/* System Control Block(SCB) modules include Memory Accelerator Module,
370	Phase Locked Loop, VPB divider, Power Control, External Interrupt,
371	Reset, and Code Security/Debugging */
372	#define SCB_BASE_ADDR 0xE01FC000
373
374	/* Memory Accelerator Module (MAM) */
375	#define MAMCR ((volatile unsigned long )(SCB_BASE_ADDR + 0x000))
376	#define MAMTIM ((volatile unsigned long )(SCB_BASE_ADDR + 0x004))
377	#define MEMMAP ((volatile unsigned long )(SCB_BASE_ADDR + 0x040))
378
379	/* Phase Locked Loop (PLL) */
380	#define PLLCON ((volatile unsigned long )(SCB_BASE_ADDR + 0x080))
381	#define PLLCFG ((volatile unsigned long )(SCB_BASE_ADDR + 0x084))
382	#define PLLSTAT ((volatile unsigned long )(SCB_BASE_ADDR + 0x088))
383	#define PLLFEED ((volatile unsigned long )(SCB_BASE_ADDR + 0x08C))
384
385	/* Power Control */
386	#define PCON ((volatile unsigned long )(SCB_BASE_ADDR + 0x0C0))
387	#define PCONP ((volatile unsigned long )(SCB_BASE_ADDR + 0x0C4))
388
389	/* Clock Divider */
390	// #define APBDIV ((volatile unsigned long )(SCB_BASE_ADDR + 0x100))
391	#define CCLKCFG ((volatile unsigned long )(SCB_BASE_ADDR + 0x104))
392	#define USBCLKCFG ((volatile unsigned long )(SCB_BASE_ADDR + 0x108))
393	#define CLKSRCSEL ((volatile unsigned long )(SCB_BASE_ADDR + 0x10C))
394	#define PCLKSEL0 ((volatile unsigned long )(SCB_BASE_ADDR + 0x1A8))
395	#define PCLKSEL1 ((volatile unsigned long )(SCB_BASE_ADDR + 0x1AC))
396
397	/* External Interrupts */
398	#define EXTINT ((volatile unsigned long )(SCB_BASE_ADDR + 0x140))
399	#define INTWAKE ((volatile unsigned long )(SCB_BASE_ADDR + 0x144))
400	#define EXTMODE ((volatile unsigned long )(SCB_BASE_ADDR + 0x148))
401	#define EXTPOLAR ((volatile unsigned long )(SCB_BASE_ADDR + 0x14C))
402
403	/* Reset, reset source identification */
404	#define RSIR ((volatile unsigned long )(SCB_BASE_ADDR + 0x180))
405
406	/* RSID, code security protection */
407	#define CSPR ((volatile unsigned long )(SCB_BASE_ADDR + 0x184))
408
409	/* AHB configuration */
410	#define AHBCFG1 ((volatile unsigned long )(SCB_BASE_ADDR + 0x188))
411	#define AHBCFG2 ((volatile unsigned long )(SCB_BASE_ADDR + 0x18C))
412
413	/* System Controls and Status */
414	#define SCS ((volatile unsigned long )(SCB_BASE_ADDR + 0x1A0))
415
416	/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
417	are for LPC24xx only. */
418	#define STATIC_MEM0_BASE 0x80000000
419	#define STATIC_MEM1_BASE 0x81000000
420	#define STATIC_MEM2_BASE 0x82000000
421	#define STATIC_MEM3_BASE 0x83000000
422
423	#define DYNAMIC_MEM0_BASE 0xA0000000
424	#define DYNAMIC_MEM1_BASE 0xB0000000
425	#define DYNAMIC_MEM2_BASE 0xC0000000
426	#define DYNAMIC_MEM3_BASE 0xD0000000
427
428	/* External Memory Controller (EMC) */
429	#define EMC_BASE_ADDR 0xFFE08000
430	#define EMC_CTRL ((volatile unsigned long )(EMC_BASE_ADDR + 0x000))
431	#define EMC_STAT ((volatile unsigned long )(EMC_BASE_ADDR + 0x004))
432	#define EMC_CONFIG ((volatile unsigned long )(EMC_BASE_ADDR + 0x008))
433
434	/* Dynamic RAM access registers */
435	#define EMC_DYN_CTRL ((volatile unsigned long )(EMC_BASE_ADDR + 0x020))
436	#define EMC_DYN_RFSH ((volatile unsigned long )(EMC_BASE_ADDR + 0x024))
437	#define EMC_DYN_RD_CFG ((volatile unsigned long )(EMC_BASE_ADDR + 0x028))
438	#define EMC_DYN_RP ((volatile unsigned long )(EMC_BASE_ADDR + 0x030))
439	#define EMC_DYN_RAS ((volatile unsigned long )(EMC_BASE_ADDR + 0x034))
440	#define EMC_DYN_SREX ((volatile unsigned long )(EMC_BASE_ADDR + 0x038))
441	#define EMC_DYN_APR ((volatile unsigned long )(EMC_BASE_ADDR + 0x03C))
442	#define EMC_DYN_DAL ((volatile unsigned long )(EMC_BASE_ADDR + 0x040))
443	#define EMC_DYN_WR ((volatile unsigned long )(EMC_BASE_ADDR + 0x044))
444	#define EMC_DYN_RC ((volatile unsigned long )(EMC_BASE_ADDR + 0x048))
445	#define EMC_DYN_RFC ((volatile unsigned long )(EMC_BASE_ADDR + 0x04C))
446	#define EMC_DYN_XSR ((volatile unsigned long )(EMC_BASE_ADDR + 0x050))
447	#define EMC_DYN_RRD ((volatile unsigned long )(EMC_BASE_ADDR + 0x054))
448	#define EMC_DYN_MRD ((volatile unsigned long )(EMC_BASE_ADDR + 0x058))
449
450	#define EMC_DYN_CFG0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x100))
451	#define EMC_DYN_RASCAS0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x104))
452	#define EMC_DYN_CFG1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x140))
453	#define EMC_DYN_RASCAS1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x144))
454	#define EMC_DYN_CFG2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x160))
455	#define EMC_DYN_RASCAS2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x164))
456	#define EMC_DYN_CFG3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x180))
457	#define EMC_DYN_RASCAS3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x184))
458
459	/* static RAM access registers */
460	#define EMC_STA_CFG0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x200))
461	#define EMC_STA_WAITWEN0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x204))
462	#define EMC_STA_WAITOEN0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x208))
463	#define EMC_STA_WAITRD0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x20C))
464	#define EMC_STA_WAITPAGE0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x210))
465	#define EMC_STA_WAITWR0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x214))
466	#define EMC_STA_WAITTURN0 ((volatile unsigned long )(EMC_BASE_ADDR + 0x218))
467
468	#define EMC_STA_CFG1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x220))
469	#define EMC_STA_WAITWEN1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x224))
470	#define EMC_STA_WAITOEN1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x228))
471	#define EMC_STA_WAITRD1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x22C))
472	#define EMC_STA_WAITPAGE1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x230))
473	#define EMC_STA_WAITWR1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x234))
474	#define EMC_STA_WAITTURN1 ((volatile unsigned long )(EMC_BASE_ADDR + 0x238))
475
476	#define EMC_STA_CFG2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x240))
477	#define EMC_STA_WAITWEN2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x244))
478	#define EMC_STA_WAITOEN2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x248))
479	#define EMC_STA_WAITRD2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x24C))
480	#define EMC_STA_WAITPAGE2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x250))
481	#define EMC_STA_WAITWR2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x254))
482	#define EMC_STA_WAITTURN2 ((volatile unsigned long )(EMC_BASE_ADDR + 0x258))
483
484	#define EMC_STA_CFG3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x260))
485	#define EMC_STA_WAITWEN3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x264))
486	#define EMC_STA_WAITOEN3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x268))
487	#define EMC_STA_WAITRD3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x26C))
488	#define EMC_STA_WAITPAGE3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x270))
489	#define EMC_STA_WAITWR3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x274))
490	#define EMC_STA_WAITTURN3 ((volatile unsigned long )(EMC_BASE_ADDR + 0x278))
491
492	#define EMC_STA_EXT_WAIT ((volatile unsigned long )(EMC_BASE_ADDR + 0x880))
493
494
495	/* Timer 0 */
496	#define TMR0_BASE_ADDR 0xE0004000
497	#define T0IR ((volatile unsigned long )(TMR0_BASE_ADDR + 0x00))
498	#define T0TCR ((volatile unsigned long )(TMR0_BASE_ADDR + 0x04))
499	#define T0TC ((volatile unsigned long )(TMR0_BASE_ADDR + 0x08))
500	#define T0PR ((volatile unsigned long )(TMR0_BASE_ADDR + 0x0C))
501	#define T0PC ((volatile unsigned long )(TMR0_BASE_ADDR + 0x10))
502	#define T0MCR ((volatile unsigned long )(TMR0_BASE_ADDR + 0x14))
503	#define T0MR0 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x18))
504	#define T0MR1 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x1C))
505	#define T0MR2 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x20))
506	#define T0MR3 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x24))
507	#define T0CCR ((volatile unsigned long )(TMR0_BASE_ADDR + 0x28))
508	#define T0CR0 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x2C))
509	#define T0CR1 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x30))
510	#define T0CR2 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x34))
511	#define T0CR3 ((volatile unsigned long )(TMR0_BASE_ADDR + 0x38))
512	#define T0EMR ((volatile unsigned long )(TMR0_BASE_ADDR + 0x3C))
513	#define T0CTCR ((volatile unsigned long )(TMR0_BASE_ADDR + 0x70))
514
515	/* Timer 1 */
516	#define TMR1_BASE_ADDR 0xE0008000
517	#define T1IR ((volatile unsigned long )(TMR1_BASE_ADDR + 0x00))
518	#define T1TCR ((volatile unsigned long )(TMR1_BASE_ADDR + 0x04))
519	#define T1TC ((volatile unsigned long )(TMR1_BASE_ADDR + 0x08))
520	#define T1PR ((volatile unsigned long )(TMR1_BASE_ADDR + 0x0C))
521	#define T1PC ((volatile unsigned long )(TMR1_BASE_ADDR + 0x10))
522	#define T1MCR ((volatile unsigned long )(TMR1_BASE_ADDR + 0x14))
523	#define T1MR0 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x18))
524	#define T1MR1 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x1C))
525	#define T1MR2 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x20))
526	#define T1MR3 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x24))
527	#define T1CCR ((volatile unsigned long )(TMR1_BASE_ADDR + 0x28))
528	#define T1CR0 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x2C))
529	#define T1CR1 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x30))
530	#define T1CR2 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x34))
531	#define T1CR3 ((volatile unsigned long )(TMR1_BASE_ADDR + 0x38))
532	#define T1EMR ((volatile unsigned long )(TMR1_BASE_ADDR + 0x3C))
533	#define T1CTCR ((volatile unsigned long )(TMR1_BASE_ADDR + 0x70))
534
535	/* Timer 2 */
536	#define TMR2_BASE_ADDR 0xE0070000
537	#define T2IR ((volatile unsigned long )(TMR2_BASE_ADDR + 0x00))
538	#define T2TCR ((volatile unsigned long )(TMR2_BASE_ADDR + 0x04))
539	#define T2TC ((volatile unsigned long )(TMR2_BASE_ADDR + 0x08))
540	#define T2PR ((volatile unsigned long )(TMR2_BASE_ADDR + 0x0C))
541	#define T2PC ((volatile unsigned long )(TMR2_BASE_ADDR + 0x10))
542	#define T2MCR ((volatile unsigned long )(TMR2_BASE_ADDR + 0x14))
543	#define T2MR0 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x18))
544	#define T2MR1 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x1C))
545	#define T2MR2 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x20))
546	#define T2MR3 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x24))
547	#define T2CCR ((volatile unsigned long )(TMR2_BASE_ADDR + 0x28))
548	#define T2CR0 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x2C))
549	#define T2CR1 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x30))
550	#define T2CR2 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x34))
551	#define T2CR3 ((volatile unsigned long )(TMR2_BASE_ADDR + 0x38))
552	#define T2EMR ((volatile unsigned long )(TMR2_BASE_ADDR + 0x3C))
553	#define T2CTCR ((volatile unsigned long )(TMR2_BASE_ADDR + 0x70))
554
555	/* Timer 3 */
556	#define TMR3_BASE_ADDR 0xE0074000
557	#define T3IR ((volatile unsigned long )(TMR3_BASE_ADDR + 0x00))
558	#define T3TCR ((volatile unsigned long )(TMR3_BASE_ADDR + 0x04))
559	#define T3TC ((volatile unsigned long )(TMR3_BASE_ADDR + 0x08))
560	#define T3PR ((volatile unsigned long )(TMR3_BASE_ADDR + 0x0C))
561	#define T3PC ((volatile unsigned long )(TMR3_BASE_ADDR + 0x10))
562	#define T3MCR ((volatile unsigned long )(TMR3_BASE_ADDR + 0x14))
563	#define T3MR0 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x18))
564	#define T3MR1 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x1C))
565	#define T3MR2 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x20))
566	#define T3MR3 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x24))
567	#define T3CCR ((volatile unsigned long )(TMR3_BASE_ADDR + 0x28))
568	#define T3CR0 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x2C))
569	#define T3CR1 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x30))
570	#define T3CR2 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x34))
571	#define T3CR3 ((volatile unsigned long )(TMR3_BASE_ADDR + 0x38))
572	#define T3EMR ((volatile unsigned long )(TMR3_BASE_ADDR + 0x3C))
573	#define T3CTCR ((volatile unsigned long )(TMR3_BASE_ADDR + 0x70))
574
575
576	/* Pulse Width Modulator (PWM) */
577	#define PWM0_BASE_ADDR 0xE0014000
578	#define PWM0IR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x00))
579	#define PWM0TCR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x04))
580	#define PWM0TC ((volatile unsigned long )(PWM0_BASE_ADDR + 0x08))
581	#define PWM0PR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x0C))
582	#define PWM0PC ((volatile unsigned long )(PWM0_BASE_ADDR + 0x10))
583	#define PWM0MCR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x14))
584	#define PWM0MR0 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x18))
585	#define PWM0MR1 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x1C))
586	#define PWM0MR2 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x20))
587	#define PWM0MR3 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x24))
588	#define PWM0CCR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x28))
589	#define PWM0CR0 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x2C))
590	#define PWM0CR1 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x30))
591	#define PWM0CR2 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x34))
592	#define PWM0CR3 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x38))
593	#define PWM0EMR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x3C))
594	#define PWM0MR4 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x40))
595	#define PWM0MR5 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x44))
596	#define PWM0MR6 ((volatile unsigned long )(PWM0_BASE_ADDR + 0x48))
597	#define PWM0PCR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x4C))
598	#define PWM0LER ((volatile unsigned long )(PWM0_BASE_ADDR + 0x50))
599	#define PWM0CTCR ((volatile unsigned long )(PWM0_BASE_ADDR + 0x70))
600
601	#define PWM1_BASE_ADDR 0xE0018000
602	#define PWM1IR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x00))
603	#define PWM1TCR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x04))
604	#define PWM1TC ((volatile unsigned long )(PWM1_BASE_ADDR + 0x08))
605	#define PWM1PR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x0C))
606	#define PWM1PC ((volatile unsigned long )(PWM1_BASE_ADDR + 0x10))
607	#define PWM1MCR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x14))
608	#define PWM1MR0 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x18))
609	#define PWM1MR1 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x1C))
610	#define PWM1MR2 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x20))
611	#define PWM1MR3 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x24))
612	#define PWM1CCR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x28))
613	#define PWM1CR0 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x2C))
614	#define PWM1CR1 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x30))
615	#define PWM1CR2 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x34))
616	#define PWM1CR3 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x38))
617	#define PWM1EMR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x3C))
618	#define PWM1MR4 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x40))
619	#define PWM1MR5 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x44))
620	#define PWM1MR6 ((volatile unsigned long )(PWM1_BASE_ADDR + 0x48))
621	#define PWM1PCR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x4C))
622	#define PWM1LER ((volatile unsigned long )(PWM1_BASE_ADDR + 0x50))
623	#define PWM1CTCR ((volatile unsigned long )(PWM1_BASE_ADDR + 0x70))
624
625
626	/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
627	#define UART0_BASE_ADDR 0xE000C000
628	#define U0RBR ((volatile unsigned long )(UART0_BASE_ADDR + 0x00))
629	#define U0THR ((volatile unsigned long )(UART0_BASE_ADDR + 0x00))
630	#define U0DLL ((volatile unsigned long )(UART0_BASE_ADDR + 0x00))
631	#define U0DLM ((volatile unsigned long )(UART0_BASE_ADDR + 0x04))
632	#define U0IER ((volatile unsigned long )(UART0_BASE_ADDR + 0x04))
633	#define U0IIR ((volatile unsigned long )(UART0_BASE_ADDR + 0x08))
634	#define U0FCR ((volatile unsigned long )(UART0_BASE_ADDR + 0x08))
635	#define U0LCR ((volatile unsigned long )(UART0_BASE_ADDR + 0x0C))
636	#define U0LSR ((volatile unsigned long )(UART0_BASE_ADDR + 0x14))
637	#define U0SCR ((volatile unsigned long )(UART0_BASE_ADDR + 0x1C))
638	#define U0ACR ((volatile unsigned long )(UART0_BASE_ADDR + 0x20))
639	#define U0ICR ((volatile unsigned long )(UART0_BASE_ADDR + 0x24))
640	#define U0FDR ((volatile unsigned long )(UART0_BASE_ADDR + 0x28))
641	#define U0TER ((volatile unsigned long )(UART0_BASE_ADDR + 0x30))
642
643	/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
644	#define UART1_BASE_ADDR 0xE0010000
645	#define U1RBR ((volatile unsigned long )(UART1_BASE_ADDR + 0x00))
646	#define U1THR ((volatile unsigned long )(UART1_BASE_ADDR + 0x00))
647	#define U1DLL ((volatile unsigned long )(UART1_BASE_ADDR + 0x00))
648	#define U1DLM ((volatile unsigned long )(UART1_BASE_ADDR + 0x04))
649	#define U1IER ((volatile unsigned long )(UART1_BASE_ADDR + 0x04))
650	#define U1IIR ((volatile unsigned long )(UART1_BASE_ADDR + 0x08))
651	#define U1FCR ((volatile unsigned long )(UART1_BASE_ADDR + 0x08))
652	#define U1LCR ((volatile unsigned long )(UART1_BASE_ADDR + 0x0C))
653	#define U1MCR ((volatile unsigned long )(UART1_BASE_ADDR + 0x10))
654	#define U1LSR ((volatile unsigned long )(UART1_BASE_ADDR + 0x14))
655	#define U1MSR ((volatile unsigned long )(UART1_BASE_ADDR + 0x18))
656	#define U1SCR ((volatile unsigned long )(UART1_BASE_ADDR + 0x1C))
657	#define U1ACR ((volatile unsigned long )(UART1_BASE_ADDR + 0x20))
658	#define U1FDR ((volatile unsigned long )(UART1_BASE_ADDR + 0x28))
659	#define U1TER ((volatile unsigned long )(UART1_BASE_ADDR + 0x30))
660
661	/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
662	#define UART2_BASE_ADDR 0xE0078000
663	#define U2RBR ((volatile unsigned long )(UART2_BASE_ADDR + 0x00))
664	#define U2THR ((volatile unsigned long )(UART2_BASE_ADDR + 0x00))
665	#define U2DLL ((volatile unsigned long )(UART2_BASE_ADDR + 0x00))
666	#define U2DLM ((volatile unsigned long )(UART2_BASE_ADDR + 0x04))
667	#define U2IER ((volatile unsigned long )(UART2_BASE_ADDR + 0x04))
668	#define U2IIR ((volatile unsigned long )(UART2_BASE_ADDR + 0x08))
669	#define U2FCR ((volatile unsigned long )(UART2_BASE_ADDR + 0x08))
670	#define U2LCR ((volatile unsigned long )(UART2_BASE_ADDR + 0x0C))
671	#define U2LSR ((volatile unsigned long )(UART2_BASE_ADDR + 0x14))
672	#define U2SCR ((volatile unsigned long )(UART2_BASE_ADDR + 0x1C))
673	#define U2ACR ((volatile unsigned long )(UART2_BASE_ADDR + 0x20))
674	#define U2ICR ((volatile unsigned long )(UART2_BASE_ADDR + 0x24))
675	#define U2FDR ((volatile unsigned long )(UART2_BASE_ADDR + 0x28))
676	#define U2TER ((volatile unsigned long )(UART2_BASE_ADDR + 0x30))
677
678	/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
679	#define UART3_BASE_ADDR 0xE007C000
680	#define U3RBR ((volatile unsigned long )(UART3_BASE_ADDR + 0x00))
681	#define U3THR ((volatile unsigned long )(UART3_BASE_ADDR + 0x00))
682	#define U3DLL ((volatile unsigned long )(UART3_BASE_ADDR + 0x00))
683	#define U3DLM ((volatile unsigned long )(UART3_BASE_ADDR + 0x04))
684	#define U3IER ((volatile unsigned long )(UART3_BASE_ADDR + 0x04))
685	#define U3IIR ((volatile unsigned long )(UART3_BASE_ADDR + 0x08))
686	#define U3FCR ((volatile unsigned long )(UART3_BASE_ADDR + 0x08))
687	#define U3LCR ((volatile unsigned long )(UART3_BASE_ADDR + 0x0C))
688	#define U3LSR ((volatile unsigned long )(UART3_BASE_ADDR + 0x14))
689	#define U3SCR ((volatile unsigned long )(UART3_BASE_ADDR + 0x1C))
690	#define U3ACR ((volatile unsigned long )(UART3_BASE_ADDR + 0x20))
691	#define U3ICR ((volatile unsigned long )(UART3_BASE_ADDR + 0x24))
692	#define U3FDR ((volatile unsigned long )(UART3_BASE_ADDR + 0x28))
693	#define U3TER ((volatile unsigned long )(UART3_BASE_ADDR + 0x30))
694
695	/* I2C Interface 0 */
696	#define I2C0_BASE_ADDR 0xE001C000
697	#define I20CONSET ((volatile unsigned long )(I2C0_BASE_ADDR + 0x00))
698	#define I20STAT ((volatile unsigned long )(I2C0_BASE_ADDR + 0x04))
699	#define I20DAT ((volatile unsigned long )(I2C0_BASE_ADDR + 0x08))
700	#define I20ADR ((volatile unsigned long )(I2C0_BASE_ADDR + 0x0C))
701	#define I20SCLH ((volatile unsigned long )(I2C0_BASE_ADDR + 0x10))
702	#define I20SCLL ((volatile unsigned long )(I2C0_BASE_ADDR + 0x14))
703	#define I20CONCLR ((volatile unsigned long )(I2C0_BASE_ADDR + 0x18))
704
705	/* I2C Interface 1 */
706	#define I2C1_BASE_ADDR 0xE005C000
707	#define I21CONSET ((volatile unsigned long )(I2C1_BASE_ADDR + 0x00))
708	#define I21STAT ((volatile unsigned long )(I2C1_BASE_ADDR + 0x04))
709	#define I21DAT ((volatile unsigned long )(I2C1_BASE_ADDR + 0x08))
710	#define I21ADR ((volatile unsigned long )(I2C1_BASE_ADDR + 0x0C))
711	#define I21SCLH ((volatile unsigned long )(I2C1_BASE_ADDR + 0x10))
712	#define I21SCLL ((volatile unsigned long )(I2C1_BASE_ADDR + 0x14))
713	#define I21CONCLR ((volatile unsigned long )(I2C1_BASE_ADDR + 0x18))
714
715	/* I2C Interface 2 */
716	#define I2C2_BASE_ADDR 0xE0080000
717	#define I22CONSET ((volatile unsigned long )(I2C2_BASE_ADDR + 0x00))
718	#define I22STAT ((volatile unsigned long )(I2C2_BASE_ADDR + 0x04))
719	#define I22DAT ((volatile unsigned long )(I2C2_BASE_ADDR + 0x08))
720	#define I22ADR ((volatile unsigned long )(I2C2_BASE_ADDR + 0x0C))
721	#define I22SCLH ((volatile unsigned long )(I2C2_BASE_ADDR + 0x10))
722	#define I22SCLL ((volatile unsigned long )(I2C2_BASE_ADDR + 0x14))
723	#define I22CONCLR ((volatile unsigned long )(I2C2_BASE_ADDR + 0x18))
724
725	/* SPI0 (Serial Peripheral Interface 0) */
726	#define SPI0_BASE_ADDR 0xE0020000
727	#define S0SPCR ((volatile unsigned long )(SPI0_BASE_ADDR + 0x00))
728	#define S0SPSR ((volatile unsigned long )(SPI0_BASE_ADDR + 0x04))
729	#define S0SPDR ((volatile unsigned long )(SPI0_BASE_ADDR + 0x08))
730	#define S0SPCCR ((volatile unsigned long )(SPI0_BASE_ADDR + 0x0C))
731	#define S0SPINT ((volatile unsigned long )(SPI0_BASE_ADDR + 0x1C))
732
733	/* SSP0 Controller */
734	#define SSP0_BASE_ADDR 0xE0068000
735	#define SSP0CR0 ((volatile unsigned long )(SSP0_BASE_ADDR + 0x00))
736	#define SSP0CR1 ((volatile unsigned long )(SSP0_BASE_ADDR + 0x04))
737	#define SSP0DR ((volatile unsigned long )(SSP0_BASE_ADDR + 0x08))
738	#define SSP0SR ((volatile unsigned long )(SSP0_BASE_ADDR + 0x0C))
739	#define SSP0CPSR ((volatile unsigned long )(SSP0_BASE_ADDR + 0x10))
740	#define SSP0IMSC ((volatile unsigned long )(SSP0_BASE_ADDR + 0x14))
741	#define SSP0RIS ((volatile unsigned long )(SSP0_BASE_ADDR + 0x18))
742	#define SSP0MIS ((volatile unsigned long )(SSP0_BASE_ADDR + 0x1C))
743	#define SSP0ICR ((volatile unsigned long )(SSP0_BASE_ADDR + 0x20))
744	#define SSP0DMACR ((volatile unsigned long )(SSP0_BASE_ADDR + 0x24))
745
746	/* SSP1 Controller */
747	#define SSP1_BASE_ADDR 0xE0030000
748	#define SSP1CR0 ((volatile unsigned long )(SSP1_BASE_ADDR + 0x00))
749	#define SSP1CR1 ((volatile unsigned long )(SSP1_BASE_ADDR + 0x04))
750	#define SSP1DR ((volatile unsigned long )(SSP1_BASE_ADDR + 0x08))
751	#define SSP1SR ((volatile unsigned long )(SSP1_BASE_ADDR + 0x0C))
752	#define SSP1CPSR ((volatile unsigned long )(SSP1_BASE_ADDR + 0x10))
753	#define SSP1IMSC ((volatile unsigned long )(SSP1_BASE_ADDR + 0x14))
754	#define SSP1RIS ((volatile unsigned long )(SSP1_BASE_ADDR + 0x18))
755	#define SSP1MIS ((volatile unsigned long )(SSP1_BASE_ADDR + 0x1C))
756	#define SSP1ICR ((volatile unsigned long )(SSP1_BASE_ADDR + 0x20))
757	#define SSP1DMACR ((volatile unsigned long )(SSP1_BASE_ADDR + 0x24))
758
759
760	/* Real Time Clock */
761	#define RTC_BASE_ADDR 0xE0024000
762	#define RTC_ILR ((volatile unsigned long )(RTC_BASE_ADDR + 0x00))
763	#define RTC_CTC ((volatile unsigned long )(RTC_BASE_ADDR + 0x04))
764	#define RTC_CCR ((volatile unsigned long )(RTC_BASE_ADDR + 0x08))
765	#define RTC_CIIR ((volatile unsigned long )(RTC_BASE_ADDR + 0x0C))
766	#define RTC_AMR ((volatile unsigned long )(RTC_BASE_ADDR + 0x10))
767	#define RTC_CTIME0 ((volatile unsigned long )(RTC_BASE_ADDR + 0x14))
768	#define RTC_CTIME1 ((volatile unsigned long )(RTC_BASE_ADDR + 0x18))
769	#define RTC_CTIME2 ((volatile unsigned long )(RTC_BASE_ADDR + 0x1C))
770	#define RTC_SEC ((volatile unsigned long )(RTC_BASE_ADDR + 0x20))
771	#define RTC_MIN ((volatile unsigned long )(RTC_BASE_ADDR + 0x24))
772	#define RTC_HOUR ((volatile unsigned long )(RTC_BASE_ADDR + 0x28))
773	#define RTC_DOM ((volatile unsigned long )(RTC_BASE_ADDR + 0x2C))
774	#define RTC_DOW ((volatile unsigned long )(RTC_BASE_ADDR + 0x30))
775	#define RTC_DOY ((volatile unsigned long )(RTC_BASE_ADDR + 0x34))
776	#define RTC_MONTH ((volatile unsigned long )(RTC_BASE_ADDR + 0x38))
777	#define RTC_YEAR ((volatile unsigned long )(RTC_BASE_ADDR + 0x3C))
778	#define RTC_CISS ((volatile unsigned long )(RTC_BASE_ADDR + 0x40))
779	#define RTC_ALSEC ((volatile unsigned long )(RTC_BASE_ADDR + 0x60))
780	#define RTC_ALMIN ((volatile unsigned long )(RTC_BASE_ADDR + 0x64))
781	#define RTC_ALHOUR ((volatile unsigned long )(RTC_BASE_ADDR + 0x68))
782	#define RTC_ALDOM ((volatile unsigned long )(RTC_BASE_ADDR + 0x6C))
783	#define RTC_ALDOW ((volatile unsigned long )(RTC_BASE_ADDR + 0x70))
784	#define RTC_ALDOY ((volatile unsigned long )(RTC_BASE_ADDR + 0x74))
785	#define RTC_ALMON ((volatile unsigned long )(RTC_BASE_ADDR + 0x78))
786	#define RTC_ALYEAR ((volatile unsigned long )(RTC_BASE_ADDR + 0x7C))
787	#define RTC_PREINT ((volatile unsigned long )(RTC_BASE_ADDR + 0x80))
788	#define RTC_PREFRAC ((volatile unsigned long )(RTC_BASE_ADDR + 0x84))
789
790
791	/* A/D Converter 0 (AD0) */
792	#define AD0_BASE_ADDR 0xE0034000
793	#define AD0CR ((volatile unsigned long )(AD0_BASE_ADDR + 0x00))
794	#define AD0GDR ((volatile unsigned long )(AD0_BASE_ADDR + 0x04))
795	#define AD0INTEN ((volatile unsigned long )(AD0_BASE_ADDR + 0x0C))
796	#define AD0DR0 ((volatile unsigned long )(AD0_BASE_ADDR + 0x10))
797	#define AD0DR1 ((volatile unsigned long )(AD0_BASE_ADDR + 0x14))
798	#define AD0DR2 ((volatile unsigned long )(AD0_BASE_ADDR + 0x18))
799	#define AD0DR3 ((volatile unsigned long )(AD0_BASE_ADDR + 0x1C))
800	#define AD0DR4 ((volatile unsigned long )(AD0_BASE_ADDR + 0x20))
801	#define AD0DR5 ((volatile unsigned long )(AD0_BASE_ADDR + 0x24))
802	#define AD0DR6 ((volatile unsigned long )(AD0_BASE_ADDR + 0x28))
803	#define AD0DR7 ((volatile unsigned long )(AD0_BASE_ADDR + 0x2C))
804	#define AD0STAT ((volatile unsigned long )(AD0_BASE_ADDR + 0x30))
805
806
807	/* D/A Converter */
808	#define DAC_BASE_ADDR 0xE006C000
809	#define DACR ((volatile unsigned long )(DAC_BASE_ADDR + 0x00))
810
811
812	/* Watchdog */
813	#define WDG_BASE_ADDR 0xE0000000
814	#define WDMOD ((volatile unsigned long )(WDG_BASE_ADDR + 0x00))
815	#define WDTC ((volatile unsigned long )(WDG_BASE_ADDR + 0x04))
816	#define WDFEED ((volatile unsigned long )(WDG_BASE_ADDR + 0x08))
817	#define WDTV ((volatile unsigned long )(WDG_BASE_ADDR + 0x0C))
818	#define WDCLKSEL ((volatile unsigned long )(WDG_BASE_ADDR + 0x10))
819
820	/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
821	#define CAN_ACCEPT_BASE_ADDR 0xE003C000
822	#define CAN_AFMR ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x00))
823	#define CAN_SFF_SA ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x04))
824	#define CAN_SFF_GRP_SA ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x08))
825	#define CAN_EFF_SA ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x0C))
826	#define CAN_EFF_GRP_SA ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x10))
827	#define CAN_EOT ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x14))
828	#define CAN_LUT_ERR_ADR ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x18))
829	#define CAN_LUT_ERR ((volatile unsigned long )(CAN_ACCEPT_BASE_ADDR + 0x1C))
830
831	#define CAN_CENTRAL_BASE_ADDR 0xE0040000
832	#define CAN_TX_SR ((volatile unsigned long )(CAN_CENTRAL_BASE_ADDR + 0x00))
833	#define CAN_RX_SR ((volatile unsigned long )(CAN_CENTRAL_BASE_ADDR + 0x04))
834	#define CAN_MSR ((volatile unsigned long )(CAN_CENTRAL_BASE_ADDR + 0x08))
835
836	#define CAN1_BASE_ADDR 0xE0044000
837	#define CAN1MOD ((volatile unsigned long )(CAN1_BASE_ADDR + 0x00))
838	#define CAN1CMR ((volatile unsigned long )(CAN1_BASE_ADDR + 0x04))
839	#define CAN1GSR ((volatile unsigned long )(CAN1_BASE_ADDR + 0x08))
840	#define CAN1ICR ((volatile unsigned long )(CAN1_BASE_ADDR + 0x0C))
841	#define CAN1IER ((volatile unsigned long )(CAN1_BASE_ADDR + 0x10))
842	#define CAN1BTR ((volatile unsigned long )(CAN1_BASE_ADDR + 0x14))
843	#define CAN1EWL ((volatile unsigned long )(CAN1_BASE_ADDR + 0x18))
844	#define CAN1SR ((volatile unsigned long )(CAN1_BASE_ADDR + 0x1C))
845	#define CAN1RFS ((volatile unsigned long )(CAN1_BASE_ADDR + 0x20))
846	#define CAN1RID ((volatile unsigned long )(CAN1_BASE_ADDR + 0x24))
847	#define CAN1RDA ((volatile unsigned long )(CAN1_BASE_ADDR + 0x28))
848	#define CAN1RDB ((volatile unsigned long )(CAN1_BASE_ADDR + 0x2C))
849
850	#define CAN1TFI1 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x30))
851	#define CAN1TID1 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x34))
852	#define CAN1TDA1 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x38))
853	#define CAN1TDB1 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x3C))
854	#define CAN1TFI2 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x40))
855	#define CAN1TID2 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x44))
856	#define CAN1TDA2 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x48))
857	#define CAN1TDB2 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x4C))
858	#define CAN1TFI3 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x50))
859	#define CAN1TID3 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x54))
860	#define CAN1TDA3 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x58))
861	#define CAN1TDB3 ((volatile unsigned long )(CAN1_BASE_ADDR + 0x5C))
862
863	#define CAN2_BASE_ADDR 0xE0048000
864	#define CAN2MOD ((volatile unsigned long )(CAN2_BASE_ADDR + 0x00))
865	#define CAN2CMR ((volatile unsigned long )(CAN2_BASE_ADDR + 0x04))
866	#define CAN2GSR ((volatile unsigned long )(CAN2_BASE_ADDR + 0x08))
867	#define CAN2ICR ((volatile unsigned long )(CAN2_BASE_ADDR + 0x0C))
868	#define CAN2IER ((volatile unsigned long )(CAN2_BASE_ADDR + 0x10))
869	#define CAN2BTR ((volatile unsigned long )(CAN2_BASE_ADDR + 0x14))
870	#define CAN2EWL ((volatile unsigned long )(CAN2_BASE_ADDR + 0x18))
871	#define CAN2SR ((volatile unsigned long )(CAN2_BASE_ADDR + 0x1C))
872	#define CAN2RFS ((volatile unsigned long )(CAN2_BASE_ADDR + 0x20))
873	#define CAN2RID ((volatile unsigned long )(CAN2_BASE_ADDR + 0x24))
874	#define CAN2RDA ((volatile unsigned long )(CAN2_BASE_ADDR + 0x28))
875	#define CAN2RDB ((volatile unsigned long )(CAN2_BASE_ADDR + 0x2C))
876
877	#define CAN2TFI1 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x30))
878	#define CAN2TID1 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x34))
879	#define CAN2TDA1 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x38))
880	#define CAN2TDB1 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x3C))
881	#define CAN2TFI2 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x40))
882	#define CAN2TID2 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x44))
883	#define CAN2TDA2 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x48))
884	#define CAN2TDB2 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x4C))
885	#define CAN2TFI3 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x50))
886	#define CAN2TID3 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x54))
887	#define CAN2TDA3 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x58))
888	#define CAN2TDB3 ((volatile unsigned long )(CAN2_BASE_ADDR + 0x5C))
889
890
891	/* MultiMedia Card Interface(MCI) Controller */
892	#define MCI_BASE_ADDR 0xE008C000
893	#define MCI_POWER ((volatile unsigned long )(MCI_BASE_ADDR + 0x00))
894	#define MCI_CLOCK ((volatile unsigned long )(MCI_BASE_ADDR + 0x04))
895	#define MCI_ARGUMENT ((volatile unsigned long )(MCI_BASE_ADDR + 0x08))
896	#define MCI_COMMAND ((volatile unsigned long )(MCI_BASE_ADDR + 0x0C))
897	#define MCI_RESP_CMD ((volatile unsigned long )(MCI_BASE_ADDR + 0x10))
898	#define MCI_RESP0 ((volatile unsigned long )(MCI_BASE_ADDR + 0x14))
899	#define MCI_RESP1 ((volatile unsigned long )(MCI_BASE_ADDR + 0x18))
900	#define MCI_RESP2 ((volatile unsigned long )(MCI_BASE_ADDR + 0x1C))
901	#define MCI_RESP3 ((volatile unsigned long )(MCI_BASE_ADDR + 0x20))
902	#define MCI_DATA_TMR ((volatile unsigned long )(MCI_BASE_ADDR + 0x24))
903	#define MCI_DATA_LEN ((volatile unsigned long )(MCI_BASE_ADDR + 0x28))
904	#define MCI_DATA_CTRL ((volatile unsigned long )(MCI_BASE_ADDR + 0x2C))
905	#define MCI_DATA_CNT ((volatile unsigned long )(MCI_BASE_ADDR + 0x30))
906	#define MCI_STATUS ((volatile unsigned long )(MCI_BASE_ADDR + 0x34))
907	#define MCI_CLEAR ((volatile unsigned long )(MCI_BASE_ADDR + 0x38))
908	#define MCI_MASK0 ((volatile unsigned long )(MCI_BASE_ADDR + 0x3C))
909	#define MCI_MASK1 ((volatile unsigned long )(MCI_BASE_ADDR + 0x40))
910	#define MCI_FIFO_CNT ((volatile unsigned long )(MCI_BASE_ADDR + 0x48))
911	#define MCI_FIFO ((volatile unsigned long )(MCI_BASE_ADDR + 0x80))
912
913
914	/* I2S Interface Controller (I2S) */
915	#define I2S_BASE_ADDR 0xE0088000
916	#define I2S_DAO ((volatile unsigned long )(I2S_BASE_ADDR + 0x00))
917	#define I2S_DAI ((volatile unsigned long )(I2S_BASE_ADDR + 0x04))
918	#define I2S_TX_FIFO ((volatile unsigned long )(I2S_BASE_ADDR + 0x08))
919	#define I2S_RX_FIFO ((volatile unsigned long )(I2S_BASE_ADDR + 0x0C))
920	#define I2S_STATE ((volatile unsigned long )(I2S_BASE_ADDR + 0x10))
921	#define I2S_DMA1 ((volatile unsigned long )(I2S_BASE_ADDR + 0x14))
922	#define I2S_DMA2 ((volatile unsigned long )(I2S_BASE_ADDR + 0x18))
923	#define I2S_IRQ ((volatile unsigned long )(I2S_BASE_ADDR + 0x1C))
924	#define I2S_TXRATE ((volatile unsigned long )(I2S_BASE_ADDR + 0x20))
925	#define I2S_RXRATE ((volatile unsigned long )(I2S_BASE_ADDR + 0x24))
926
927
928	/* General-purpose DMA Controller */
929	#define DMA_BASE_ADDR 0xFFE04000
930	#define GPDMA_INT_STAT ((volatile unsigned long )(DMA_BASE_ADDR + 0x000))
931	#define GPDMA_INT_TCSTAT ((volatile unsigned long )(DMA_BASE_ADDR + 0x004))
932	#define GPDMA_INT_TCCLR ((volatile unsigned long )(DMA_BASE_ADDR + 0x008))
933	#define GPDMA_INT_ERR_STAT ((volatile unsigned long )(DMA_BASE_ADDR + 0x00C))
934	#define GPDMA_INT_ERR_CLR ((volatile unsigned long )(DMA_BASE_ADDR + 0x010))
935	#define GPDMA_RAW_INT_TCSTAT ((volatile unsigned long )(DMA_BASE_ADDR + 0x014))
936	#define GPDMA_RAW_INT_ERR_STAT ((volatile unsigned long )(DMA_BASE_ADDR + 0x018))
937	#define GPDMA_ENABLED_CHNS ((volatile unsigned long )(DMA_BASE_ADDR + 0x01C))
938	#define GPDMA_SOFT_BREQ ((volatile unsigned long )(DMA_BASE_ADDR + 0x020))
939	#define GPDMA_SOFT_SREQ ((volatile unsigned long )(DMA_BASE_ADDR + 0x024))
940	#define GPDMA_SOFT_LBREQ ((volatile unsigned long )(DMA_BASE_ADDR + 0x028))
941	#define GPDMA_SOFT_LSREQ ((volatile unsigned long )(DMA_BASE_ADDR + 0x02C))
942	#define GPDMA_CONFIG ((volatile unsigned long )(DMA_BASE_ADDR + 0x030))
943	#define GPDMA_SYNC ((volatile unsigned long )(DMA_BASE_ADDR + 0x034))
944
945	/* DMA channel 0 registers */
946	#define GPDMA_CH0_SRC ((volatile unsigned long )(DMA_BASE_ADDR + 0x100))
947	#define GPDMA_CH0_DEST ((volatile unsigned long )(DMA_BASE_ADDR + 0x104))
948	#define GPDMA_CH0_LLI ((volatile unsigned long )(DMA_BASE_ADDR + 0x108))
949	#define GPDMA_CH0_CTRL ((volatile unsigned long )(DMA_BASE_ADDR + 0x10C))
950	#define GPDMA_CH0_CFG ((volatile unsigned long )(DMA_BASE_ADDR + 0x110))
951
952	/* DMA channel 1 registers */
953	#define GPDMA_CH1_SRC ((volatile unsigned long )(DMA_BASE_ADDR + 0x120))
954	#define GPDMA_CH1_DEST ((volatile unsigned long )(DMA_BASE_ADDR + 0x124))
955	#define GPDMA_CH1_LLI ((volatile unsigned long )(DMA_BASE_ADDR + 0x128))
956	#define GPDMA_CH1_CTRL ((volatile unsigned long )(DMA_BASE_ADDR + 0x12C))
957	#define GPDMA_CH1_CFG ((volatile unsigned long )(DMA_BASE_ADDR + 0x130))
958
959
960	/* USB Controller */
961	#define USB_INT_BASE_ADDR 0xE01FC1C0
962	#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
963
964	#define USB_INT_STAT ((volatile unsigned long )(USB_INT_BASE_ADDR + 0x00))
965
966	/* USB Device Interrupt Registers */
967	#define DEV_INT_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0x00))
968	#define DEV_INT_EN ((volatile unsigned long )(USB_BASE_ADDR + 0x04))
969	#define DEV_INT_CLR ((volatile unsigned long )(USB_BASE_ADDR + 0x08))
970	#define DEV_INT_SET ((volatile unsigned long )(USB_BASE_ADDR + 0x0C))
971	#define DEV_INT_PRIO ((volatile unsigned long )(USB_BASE_ADDR + 0x2C))
972
973	/* USB Device Endpoint Interrupt Registers */
974	#define EP_INT_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0x30))
975	#define EP_INT_EN ((volatile unsigned long )(USB_BASE_ADDR + 0x34))
976	#define EP_INT_CLR ((volatile unsigned long )(USB_BASE_ADDR + 0x38))
977	#define EP_INT_SET ((volatile unsigned long )(USB_BASE_ADDR + 0x3C))
978	#define EP_INT_PRIO ((volatile unsigned long )(USB_BASE_ADDR + 0x40))
979
980	/* USB Device Endpoint Realization Registers */
981	#define REALIZE_EP ((volatile unsigned long )(USB_BASE_ADDR + 0x44))
982	#define EP_INDEX ((volatile unsigned long )(USB_BASE_ADDR + 0x48))
983	#define MAXPACKET_SIZE ((volatile unsigned long )(USB_BASE_ADDR + 0x4C))
984
985	/* USB Device Command Reagisters */
986	#define CMD_CODE ((volatile unsigned long )(USB_BASE_ADDR + 0x10))
987	#define CMD_DATA ((volatile unsigned long )(USB_BASE_ADDR + 0x14))
988
989	/* USB Device Data Transfer Registers */
990	#define RX_DATA ((volatile unsigned long )(USB_BASE_ADDR + 0x18))
991	#define TX_DATA ((volatile unsigned long )(USB_BASE_ADDR + 0x1C))
992	#define RX_PLENGTH ((volatile unsigned long )(USB_BASE_ADDR + 0x20))
993	#define TX_PLENGTH ((volatile unsigned long )(USB_BASE_ADDR + 0x24))
994	#define USB_CTRL ((volatile unsigned long )(USB_BASE_ADDR + 0x28))
995
996	/* USB Device DMA Registers */
997	#define DMA_REQ_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0x50))
998	#define DMA_REQ_CLR ((volatile unsigned long )(USB_BASE_ADDR + 0x54))
999	#define DMA_REQ_SET ((volatile unsigned long )(USB_BASE_ADDR + 0x58))
1000	#define UDCA_HEAD ((volatile unsigned long )(USB_BASE_ADDR + 0x80))
1001	#define EP_DMA_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0x84))
1002	#define EP_DMA_EN ((volatile unsigned long )(USB_BASE_ADDR + 0x88))
1003	#define EP_DMA_DIS ((volatile unsigned long )(USB_BASE_ADDR + 0x8C))
1004	#define DMA_INT_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0x90))
1005	#define DMA_INT_EN ((volatile unsigned long )(USB_BASE_ADDR + 0x94))
1006	#define EOT_INT_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0xA0))
1007	#define EOT_INT_CLR ((volatile unsigned long )(USB_BASE_ADDR + 0xA4))
1008	#define EOT_INT_SET ((volatile unsigned long )(USB_BASE_ADDR + 0xA8))
1009	#define NDD_REQ_INT_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0xAC))
1010	#define NDD_REQ_INT_CLR ((volatile unsigned long )(USB_BASE_ADDR + 0xB0))
1011	#define NDD_REQ_INT_SET ((volatile unsigned long )(USB_BASE_ADDR + 0xB4))
1012	#define SYS_ERR_INT_STAT ((volatile unsigned long )(USB_BASE_ADDR + 0xB8))
1013	#define SYS_ERR_INT_CLR ((volatile unsigned long )(USB_BASE_ADDR + 0xBC))
1014	#define SYS_ERR_INT_SET ((volatile unsigned long )(USB_BASE_ADDR + 0xC0))
1015
1016	/* USB Host and OTG registers are for LPC24xx only */
1017	/* USB Host Controller */
1018	#define USBHC_BASE_ADDR 0xFFE0C000
1019	#define HC_REVISION ((volatile unsigned long )(USBHC_BASE_ADDR + 0x00))
1020	#define HC_CONTROL ((volatile unsigned long )(USBHC_BASE_ADDR + 0x04))
1021	#define HC_CMD_STAT ((volatile unsigned long )(USBHC_BASE_ADDR + 0x08))
1022	#define HC_INT_STAT ((volatile unsigned long )(USBHC_BASE_ADDR + 0x0C))
1023	#define HC_INT_EN ((volatile unsigned long )(USBHC_BASE_ADDR + 0x10))
1024	#define HC_INT_DIS ((volatile unsigned long )(USBHC_BASE_ADDR + 0x14))
1025	#define HC_HCCA ((volatile unsigned long )(USBHC_BASE_ADDR + 0x18))
1026	#define HC_PERIOD_CUR_ED ((volatile unsigned long )(USBHC_BASE_ADDR + 0x1C))
1027	#define HC_CTRL_HEAD_ED ((volatile unsigned long )(USBHC_BASE_ADDR + 0x20))
1028	#define HC_CTRL_CUR_ED ((volatile unsigned long )(USBHC_BASE_ADDR + 0x24))
1029	#define HC_BULK_HEAD_ED ((volatile unsigned long )(USBHC_BASE_ADDR + 0x28))
1030	#define HC_BULK_CUR_ED ((volatile unsigned long )(USBHC_BASE_ADDR + 0x2C))
1031	#define HC_DONE_HEAD ((volatile unsigned long )(USBHC_BASE_ADDR + 0x30))
1032	#define HC_FM_INTERVAL ((volatile unsigned long )(USBHC_BASE_ADDR + 0x34))
1033	#define HC_FM_REMAINING ((volatile unsigned long )(USBHC_BASE_ADDR + 0x38))
1034	#define HC_FM_NUMBER ((volatile unsigned long )(USBHC_BASE_ADDR + 0x3C))
1035	#define HC_PERIOD_START ((volatile unsigned long )(USBHC_BASE_ADDR + 0x40))
1036	#define HC_LS_THRHLD ((volatile unsigned long )(USBHC_BASE_ADDR + 0x44))
1037	#define HC_RH_DESCA ((volatile unsigned long )(USBHC_BASE_ADDR + 0x48))
1038	#define HC_RH_DESCB ((volatile unsigned long )(USBHC_BASE_ADDR + 0x4C))
1039	#define HC_RH_STAT ((volatile unsigned long )(USBHC_BASE_ADDR + 0x50))
1040	#define HC_RH_PORT_STAT1 ((volatile unsigned long )(USBHC_BASE_ADDR + 0x54))
1041	#define HC_RH_PORT_STAT2 ((volatile unsigned long )(USBHC_BASE_ADDR + 0x58))
1042
1043	/* USB OTG Controller */
1044	#define USBOTG_BASE_ADDR 0xFFE0C100
1045	#define OTG_INT_STAT ((volatile unsigned long )(USBOTG_BASE_ADDR + 0x00))
1046	#define OTG_INT_EN ((volatile unsigned long )(USBOTG_BASE_ADDR + 0x04))
1047	#define OTG_INT_SET ((volatile unsigned long )(USBOTG_BASE_ADDR + 0x08))
1048	#define OTG_INT_CLR ((volatile unsigned long )(USBOTG_BASE_ADDR + 0x0C))
1049	/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
1050	#define OTG_STAT_CTRL ((volatile unsigned long )(USBOTG_BASE_ADDR + 0x10))
1051	#define OTG_TIMER ((volatile unsigned long )(USBOTG_BASE_ADDR + 0x14))
1052
1053	#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
1054	#define OTG_I2C_RX ((volatile unsigned long )(USBOTG_I2C_BASE_ADDR + 0x00))
1055	#define OTG_I2C_TX ((volatile unsigned long )(USBOTG_I2C_BASE_ADDR + 0x00))
1056	#define OTG_I2C_STS ((volatile unsigned long )(USBOTG_I2C_BASE_ADDR + 0x04))
1057	#define OTG_I2C_CTL ((volatile unsigned long )(USBOTG_I2C_BASE_ADDR + 0x08))
1058	#define OTG_I2C_CLKHI ((volatile unsigned long )(USBOTG_I2C_BASE_ADDR + 0x0C))
1059	#define OTG_I2C_CLKLO ((volatile unsigned long )(USBOTG_I2C_BASE_ADDR + 0x10))
1060
1061	/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
1062	OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
1063	#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
1064	#define OTG_CLK_CTRL ((volatile unsigned long )(USBOTG_CLK_BASE_ADDR + 0x04))
1065	#define OTG_CLK_STAT ((volatile unsigned long )(USBOTG_CLK_BASE_ADDR + 0x08))
1066
1067	/* Note: below three register name convention is for LPC23xx USB device only, match
1068	with the spec. update in USB Device Section. */
1069	#define USBPortSel ((volatile unsigned long )(USBOTG_BASE_ADDR + 0x10))
1070	#define USBClkCtrl ((volatile unsigned long )(USBOTG_CLK_BASE_ADDR + 0x04))
1071	#define USBClkSt ((volatile unsigned long )(USBOTG_CLK_BASE_ADDR + 0x08))
1072
1073	/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1074	#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
1075	#define MAC_MAC1 ((volatile unsigned long )(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1076	#define MAC_MAC2 ((volatile unsigned long )(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1077	#define MAC_IPGT ((volatile unsigned long )(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1078	#define MAC_IPGR ((volatile unsigned long )(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1079	#define MAC_CLRT ((volatile unsigned long )(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1080	#define MAC_MAXF ((volatile unsigned long )(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1081	#define MAC_SUPP ((volatile unsigned long )(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1082	#define MAC_TEST ((volatile unsigned long )(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1083	#define MAC_MCFG ((volatile unsigned long )(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1084	#define MAC_MCMD ((volatile unsigned long )(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1085	#define MAC_MADR ((volatile unsigned long )(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1086	#define MAC_MWTD ((volatile unsigned long )(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1087	#define MAC_MRDD ((volatile unsigned long )(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1088	#define MAC_MIND ((volatile unsigned long )(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1089
1090	#define MAC_SA0 ((volatile unsigned long )(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1091	#define MAC_SA1 ((volatile unsigned long )(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1092	#define MAC_SA2 ((volatile unsigned long )(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1093
1094	#define MAC_COMMAND ((volatile unsigned long )(MAC_BASE_ADDR + 0x100)) /* Command reg */
1095	#define MAC_STATUS ((volatile unsigned long )(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1096	#define MAC_RXDESCRIPTOR ((volatile unsigned long )(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1097	#define MAC_RXSTATUS ((volatile unsigned long )(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1098	#define MAC_RXDESCRIPTORNUM ((volatile unsigned long )(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1099	#define MAC_RXPRODUCEINDEX ((volatile unsigned long )(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1100	#define MAC_RXCONSUMEINDEX ((volatile unsigned long )(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1101	#define MAC_TXDESCRIPTOR ((volatile unsigned long )(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1102	#define MAC_TXSTATUS ((volatile unsigned long )(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1103	#define MAC_TXDESCRIPTORNUM ((volatile unsigned long )(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1104	#define MAC_TXPRODUCEINDEX ((volatile unsigned long )(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1105	#define MAC_TXCONSUMEINDEX ((volatile unsigned long )(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1106
1107	#define MAC_TSV0 ((volatile unsigned long )(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1108	#define MAC_TSV1 ((volatile unsigned long )(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1109	#define MAC_RSV ((volatile unsigned long )(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1110
1111	#define MAC_FLOWCONTROLCNT ((volatile unsigned long )(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1112	#define MAC_FLOWCONTROLSTS ((volatile unsigned long )(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1113
1114	#define MAC_RXFILTERCTRL ((volatile unsigned long )(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1115	#define MAC_RXFILTERWOLSTS ((volatile unsigned long )(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1116	#define MAC_RXFILTERWOLCLR ((volatile unsigned long )(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1117
1118	#define MAC_HASHFILTERL ((volatile unsigned long )(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1119	#define MAC_HASHFILTERH ((volatile unsigned long )(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1120
1121	#define MAC_INTSTATUS ((volatile unsigned long )(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1122	#define MAC_INTENABLE ((volatile unsigned long )(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
1123	#define MAC_INTCLEAR ((volatile unsigned long )(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1124	#define MAC_INTSET ((volatile unsigned long )(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1125
1126	#define MAC_POWERDOWN ((volatile unsigned long )(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1127	#define MAC_MODULEID ((volatile unsigned long )(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1128
1129
1130	#endif // __LPC23xx_H
1131

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