portISR.c

Revision 14, 8.4 kB (checked in by phil, 15 years ago)
added unmodified FreeRTOS package V5.4.1 with only web srv demo source for LPC2368 for CrossWorks?

Line
1	/*
2	FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.
3
4	This file is part of the FreeRTOS distribution.
5
6	FreeRTOS is free software; you can redistribute it and/or modify it under
7	the terms of the GNU General Public License (version 2) as published by the
8	Free Software Foundation and modified by the FreeRTOS exception.
9	NOTE The exception to the GPL is included to allow you to distribute a
10	combined work that includes FreeRTOS without being obliged to provide the
11	source code for proprietary components outside of the FreeRTOS kernel.
12	Alternative commercial license and support terms are also available upon
13	request. See the licensing section of http://www.FreeRTOS.org for full
14	license details.
15
16	FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
17	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19	more details.
20
21	You should have received a copy of the GNU General Public License along
22	with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59
23	Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24
25
26	***************************************************************************
27	* *
28	* Looking for a quick start? Then check out the FreeRTOS eBook! *
29	* See http://www.FreeRTOS.org/Documentation for details *
30	* *
31	***************************************************************************
32
33	1 tab == 4 spaces!
34
35	Please ensure to read the configuration and relevant port sections of the
36	online documentation.
37
38	http://www.FreeRTOS.org - Documentation, latest information, license and
39	contact details.
40
41	http://www.SafeRTOS.com - A version that is certified for use in safety
42	critical systems.
43
44	http://www.OpenRTOS.com - Commercial support, development, porting,
45	licensing and training services.
46	*/
47
48
49	/*-----------------------------------------------------------
50	* Components that can be compiled to either ARM or THUMB mode are
51	* contained in port.c The ISR routines, which can only be compiled
52	* to ARM mode, are contained in this file.
53	----------------------------------------------------------/
54
55	/* Scheduler includes. */
56	#include "FreeRTOS.h"
57	#include "task.h"
58
59	/* Constants required to handle interrupts. */
60	#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
61	#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
62
63	/* Constants required to handle critical sections. */
64	#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
65	volatile unsigned portLONG ulCriticalNesting = 9999UL;
66
67	/-----------------------------------------------------------/
68
69	/* ISR to handle manual context switches (from a call to taskYIELD()). */
70	void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
71
72	/*
73	* The scheduler can only be started from ARM mode, hence the inclusion of this
74	* function here.
75	*/
76	void vPortISRStartFirstTask( void );
77	/-----------------------------------------------------------/
78
79	void vPortISRStartFirstTask( void )
80	{
81	/* Simply start the scheduler. This is included here as it can only be
82	called from ARM mode. */
83	portRESTORE_CONTEXT();
84	}
85	/-----------------------------------------------------------/
86
87	/*
88	* Called by portYIELD() or taskYIELD() to manually force a context switch.
89	*
90	* When a context switch is performed from the task level the saved task
91	* context is made to look as if it occurred from within the tick ISR. This
92	* way the same restore context function can be used when restoring the context
93	* saved from the ISR or that saved from a call to vPortYieldProcessor.
94	*/
95	void vPortYieldProcessor( void )
96	{
97	/* Within an IRQ ISR the link register has an offset from the true return
98	address, but an SWI ISR does not. Add the offset manually so the same
99	ISR return code can be used in both cases. */
100	asm volatile ( "ADD LR, LR, #4" );
101
102	/* Perform the context switch. First save the context of the current task. */
103	portSAVE_CONTEXT();
104
105	/* Find the highest priority task that is ready to run. */
106	vTaskSwitchContext();
107
108	/* Restore the context of the new task. */
109	portRESTORE_CONTEXT();
110	}
111	/-----------------------------------------------------------/
112
113	/*
114	* The ISR used for the scheduler tick depends on whether the cooperative or
115	* the preemptive scheduler is being used.
116	*/
117
118
119	#if configUSE_PREEMPTION == 0
120
121	/* The cooperative scheduler requires a normal IRQ service routine to
122	simply increment the system tick. */
123	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
124	void vNonPreemptiveTick( void )
125	{
126	vTaskIncrementTick();
127	T0IR = 2;
128	VICVectAddr = portCLEAR_VIC_INTERRUPT;
129	}
130
131	#else
132
133	/* The preemptive scheduler is defined as "naked" as the full context is
134	saved on entry as part of the context switch. */
135	void vPreemptiveTick( void ) __attribute__((naked));
136	void vPreemptiveTick( void )
137	{
138	/* Save the context of the interrupted task. */
139	portSAVE_CONTEXT();
140
141	/* Increment the RTOS tick count, then look for the highest priority
142	task that is ready to run. */
143	vTaskIncrementTick();
144	vTaskSwitchContext();
145
146	/* Ready for the next interrupt. */
147	T0IR = 2;
148	VICVectAddr = portCLEAR_VIC_INTERRUPT;
149
150	/* Restore the context of the new task. */
151	portRESTORE_CONTEXT();
152	}
153
154	#endif
155	/-----------------------------------------------------------/
156
157	/*
158	* The interrupt management utilities can only be called from ARM mode. When
159	* THUMB_INTERWORK is defined the utilities are defined as functions here to
160	* ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
161	* the utilities are defined as macros in portmacro.h - as per other ports.
162	*/
163	#ifdef THUMB_INTERWORK
164
165	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
166	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
167
168	void vPortDisableInterruptsFromThumb( void )
169	{
170	asm volatile (
171	"STMDB SP!, {R0} \n\t" /* Push R0. */
172	"MRS R0, CPSR \n\t" /* Get CPSR. */
173	"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
174	"MSR CPSR, R0 \n\t" /* Write back modified value. */
175	"LDMIA SP!, {R0} \n\t" /* Pop R0. */
176	"BX R14" ); /* Return back to thumb. */
177	}
178
179	void vPortEnableInterruptsFromThumb( void )
180	{
181	asm volatile (
182	"STMDB SP!, {R0} \n\t" /* Push R0. */
183	"MRS R0, CPSR \n\t" /* Get CPSR. */
184	"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
185	"MSR CPSR, R0 \n\t" /* Write back modified value. */
186	"LDMIA SP!, {R0} \n\t" /* Pop R0. */
187	"BX R14" ); /* Return back to thumb. */
188	}
189
190	#endif /* THUMB_INTERWORK */
191
192	/* The code generated by the GCC compiler uses the stack in different ways at
193	different optimisation levels. The interrupt flags can therefore not always
194	be saved to the stack. Instead the critical section nesting level is stored
195	in a variable, which is then saved as part of the stack context. */
196	void vPortEnterCritical( void )
197	{
198	/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
199	asm volatile (
200	"STMDB SP!, {R0} \n\t" /* Push R0. */
201	"MRS R0, CPSR \n\t" /* Get CPSR. */
202	"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
203	"MSR CPSR, R0 \n\t" /* Write back modified value. */
204	"LDMIA SP!, {R0}" ); /* Pop R0. */
205
206	/* Now interrupts are disabled ulCriticalNesting can be accessed
207	directly. Increment ulCriticalNesting to keep a count of how many times
208	portENTER_CRITICAL() has been called. */
209	ulCriticalNesting++;
210	}
211
212	void vPortExitCritical( void )
213	{
214	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
215	{
216	/* Decrement the nesting count as we are leaving a critical section. */
217	ulCriticalNesting--;
218
219	/* If the nesting level has reached zero then interrupts should be
220	re-enabled. */
221	if( ulCriticalNesting == portNO_CRITICAL_NESTING )
222	{
223	/* Enable interrupts as per portEXIT_CRITICAL(). */
224	asm volatile (
225	"STMDB SP!, {R0} \n\t" /* Push R0. */
226	"MRS R0, CPSR \n\t" /* Get CPSR. */
227	"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
228	"MSR CPSR, R0 \n\t" /* Write back modified value. */
229	"LDMIA SP!, {R0}" ); /* Pop R0. */
230	}
231	}
232	}

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