Changeset 15 for webserver/example

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Timestamp:
08/10/09 10:58:19 (15 years ago)
Author:
phil
Message:

adaptated ethernet driver to supplied includes

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  • webserver/example/freeRTOS/Demo/ARM7_LPC2368_Rowley/webserver/emac.c

    r14 r15  
    4242  unsigned int tout; 
    4343 
    44   MADR = DP83848C_DEF_ADR | PhyReg; 
    45   MWTD = Value; 
     44  MAC_MADR = DP83848C_DEF_ADR | PhyReg; 
     45  MAC_MWTD = Value; 
    4646 
    4747  /* Wait utill operation completed */ 
    4848  tout = 0; 
    4949  for (tout = 0; tout < MII_WR_TOUT; tout++) { 
    50     if ((MIND & MIND_BUSY) == 0) { 
     50    if ((MAC_MIND & MIND_BUSY) == 0) { 
    5151      break; 
    5252    } 
    …… 
    6060  unsigned int tout; 
    6161 
    62   MADR = DP83848C_DEF_ADR | PhyReg; 
    63   MCMD = MCMD_READ; 
     62  MAC_MADR = DP83848C_DEF_ADR | PhyReg; 
     63  MAC_MCMD = MCMD_READ; 
    6464 
    6565  /* Wait until operation completed */ 
    6666  tout = 0; 
    6767  for (tout = 0; tout < MII_RD_TOUT; tout++) { 
    68     if ((MIND & MIND_BUSY) == 0) { 
     68    if ((MAC_MIND & MIND_BUSY) == 0) { 
    6969      break; 
    7070    } 
    7171  } 
    72   MCMD = 0; 
    73   return (MRDD); 
     72  MAC_MCMD = 0; 
     73  return (MAC_MRDD); 
    7474} 
    7575 
    …… 
    8888 
    8989  /* Set EMAC Receive Descriptor Registers. */ 
    90   RxDescriptor    = RX_DESC_BASE; 
    91   RxStatus        = RX_STAT_BASE; 
    92   RxDescriptorNumber = NUM_RX_FRAG-1; 
     90  MAC_RXDESCRIPTOR    = RX_DESC_BASE; 
     91  MAC_RXSTATUS        = RX_STAT_BASE; 
     92  MAC_RXDESCRIPTORNUM = NUM_RX_FRAG-1; 
    9393 
    9494  /* Rx Descriptors Point to 0 */ 
    95   RxConsumeIndex  = 0; 
     95  MAC_RXCONSUMEINDEX  = 0; 
    9696} 
    9797 
    …… 
    108108 
    109109  /* Set EMAC Transmit Descriptor Registers. */ 
    110   TxDescriptor    = TX_DESC_BASE; 
    111   TxStatus        = TX_STAT_BASE; 
    112   TxDescriptorNumber = NUM_TX_FRAG-1; 
     110  MAC_TXDESCRIPTOR    = TX_DESC_BASE; 
     111  MAC_TXSTATUS        = TX_STAT_BASE; 
     112  MAC_TXDESCRIPTORNUM = NUM_TX_FRAG-1; 
    113113 
    114114  /* Tx Descriptors Point to 0 */ 
    115   TxProduceIndex  = 0; 
     115  MAC_TXPRODUCEINDEX  = 0; 
    116116} 
    117117 
    …… 
    137137 
    138138  /* Reset all EMAC internal modules. */ 
    139   MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | 
     139  MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | 
    140140             MAC1_SIM_RES | MAC1_SOFT_RES; 
    141   Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; 
     141  MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES; 
    142142 
    143143  /* A short delay after reset. */ 
    …… 
    145145 
    146146  /* Initialize MAC control registers. */ 
    147   MAC1 = MAC1_PASS_ALL; 
    148   MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; 
    149   MAXF = ETH_MAX_FLEN; 
    150   CLRT = CLRT_DEF; 
    151   IPGR = IPGR_DEF; 
     147  MAC_MAC1 = MAC1_PASS_ALL; 
     148  MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; 
     149  MAC_MAXF = ETH_MAX_FLEN; 
     150  MAC_CLRT = CLRT_DEF; 
     151  MAC_IPGR = IPGR_DEF; 
    152152 
    153153  /* Enable Reduced MII interface. */ 
    154   Command = CR_RMII | CR_PASS_RUNT_FRM; 
     154  MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM; 
    155155 
    156156  /* Reset Reduced MII Logic. */ 
    157   SUPP = SUPP_RES_RMII; 
    158   SUPP = 0; 
     157  MAC_SUPP = SUPP_RES_RMII; 
     158  MAC_SUPP = 0; 
    159159 
    160160  /* Put the DP83848C in reset mode */ 
    …… 
    215215    if (regv & 0x0004) { 
    216216      /* Full duplex is enabled. */ 
    217       MAC2    |= MAC2_FULL_DUP; 
    218       Command |= CR_FULL_DUP; 
    219       IPGT     = IPGT_FULL_DUP; 
     217      MAC_MAC2    |= MAC2_FULL_DUP; 
     218      MAC_COMMAND |= CR_FULL_DUP; 
     219      MAC_IPGT     = IPGT_FULL_DUP; 
    220220    } 
    221221    else { 
    222222      /* Half duplex mode. */ 
    223       IPGT = IPGT_HALF_DUP; 
     223      MAC_IPGT = IPGT_HALF_DUP; 
    224224    } 
    225225 
    …… 
    227227    if (regv & 0x0002) { 
    228228      /* 10MBit mode. */ 
    229       SUPP = 0; 
     229      MAC_SUPP = 0; 
    230230    } 
    231231    else { 
    232232      /* 100MBit mode. */ 
    233       SUPP = SUPP_SPEED; 
     233      MAC_SUPP = SUPP_SPEED; 
    234234    } 
    235235 
    236236    /* Set the Ethernet MAC Address registers */ 
    237     SA0 = (emacETHADDR0 << 8) | emacETHADDR1; 
    238     SA1 = (emacETHADDR2 << 8) | emacETHADDR3; 
    239     SA2 = (emacETHADDR4 << 8) | emacETHADDR5; 
     237    MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1; 
     238    MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3; 
     239    MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5; 
    240240 
    241241    /* Initialize Tx and Rx DMA Descriptors */ 
    …… 
    244244 
    245245    /* Receive Broadcast and Perfect Match Packets */ 
    246     RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; 
     246    MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; 
    247247 
    248248    /* Create the semaphore used ot wake the uIP task. */ 
    …… 
    250250 
    251251    /* Reset all interrupts */ 
    252     IntClear  = 0xFFFF; 
     252    MAC_INTCLEAR  = 0xFFFF; 
    253253 
    254254    /* Enable receive and transmit mode of MAC Ethernet core */ 
    255     Command  |= (CR_RX_EN | CR_TX_EN); 
    256     MAC1     |= MAC1_REC_EN; 
     255    MAC_COMMAND  |= (CR_RX_EN | CR_TX_EN); 
     256    MAC_MAC1     |= MAC1_REC_EN; 
    257257  } 
    258258 
    …… 
    319319  unsigned int idx; 
    320320 
    321   idx = RxConsumeIndex; 
     321  idx = MAC_RXCONSUMEINDEX; 
    322322  RxLen = (RX_STAT_INFO(idx) & RINFO_SIZE) - 3; 
    323323  rptr = (unsigned short *)RX_DESC_PACKET(idx); 
    …… 
    329329 
    330330  /* DMA free packet. */ 
    331   idx = RxConsumeIndex; 
     331  idx = MAC_RXCONSUMEINDEX; 
    332332 
    333333  if (++idx == NUM_RX_FRAG) 
    334334    idx = 0; 
    335335 
    336   RxConsumeIndex = idx; 
     336  MAC_RXCONSUMEINDEX = idx; 
    337337} 
    338338 
    339339unsigned int CheckFrameReceived(void) {             // Packet received ? 
    340340 
    341   if (RxProduceIndex != RxConsumeIndex)     // more packets received ? 
     341  if (MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX)     // more packets received ? 
    342342    return(1); 
    343343  else  
    …… 
    349349unsigned int uiLen = 0; 
    350350 
    351     if( RxProduceIndex != RxConsumeIndex ) 
     351    if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX ) 
    352352    { 
    353353        uiLen = StartReadFrame(); 
    …… 
    365365  unsigned int idx; 
    366366 
    367   idx  = TxProduceIndex; 
     367  idx  = MAC_TXPRODUCEINDEX; 
    368368  tptr = (unsigned short *)TX_DESC_PACKET(idx); 
    369369} 
    …… 
    405405  unsigned int idx; 
    406406 
    407   idx = TxProduceIndex; 
     407  idx = MAC_TXPRODUCEINDEX; 
    408408  TX_DESC_CTRL(idx) = FrameSize | TCTRL_LAST; 
    409409  if (++idx == NUM_TX_FRAG) idx = 0; 
    410   TxProduceIndex = idx; 
    411 } 
    412  
     410  MAC_TXPRODUCEINDEX = idx; 
     411} 
     412